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author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-22 18:52:05 -0800 |
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committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-22 18:52:05 -0800 |
commit | cdb01ab57260ef3e264f81a048d07e5130941414 (patch) | |
tree | d39840e268269b7dbcc0d7290ff8851433eb227f /test | |
parent | cc26b5be9d096825c8768f486f7e2151098915ef (diff) | |
download | sail-riscv-cdb01ab57260ef3e264f81a048d07e5130941414.zip sail-riscv-cdb01ab57260ef3e264f81a048d07e5130941414.tar.gz sail-riscv-cdb01ab57260ef3e264f81a048d07e5130941414.tar.bz2 |
Fix address translation bug in ordering of width-extension and shift in pte. This showed up in RV32, but not in RV64, presumably because the highest address bits are not typically exercised typical physical memory maps.
Diffstat (limited to 'test')
-rwxr-xr-x | test/run_tests.sh | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/test/run_tests.sh b/test/run_tests.sh index 0a3da0d..e548638 100755 --- a/test/run_tests.sh +++ b/test/run_tests.sh @@ -61,8 +61,7 @@ else red "Building 32-bit RISCV specification" "fail" fi -for test in $DIR/riscv-tests/rv32*-p-*.elf; do - echo Testing $test +for test in $DIR/riscv-tests/rv32*.elf; do if $RISCVDIR/ocaml_emulator/riscv_ocaml_sim "$test" >"${test/.elf/.out}" 2>&1 && grep -q SUCCESS "${test/.elf/.out}" then green "$(basename $test)" "ok" |