diff options
author | Robert Norton <rmn30@cam.ac.uk> | 2018-11-30 12:24:33 +0000 |
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committer | Robert Norton <rmn30@cam.ac.uk> | 2018-11-30 12:24:33 +0000 |
commit | c18905486156fe245ba4edbddf3c41d475382eeb (patch) | |
tree | 882ba8f7087a6fa7770f9f7d85567e73fc91ffc1 /test/tests/disabled | |
parent | d4ebbe4f3f32ea10082009fb93f0c3fbf9c56c97 (diff) | |
download | sail-riscv-c18905486156fe245ba4edbddf3c41d475382eeb.zip sail-riscv-c18905486156fe245ba4edbddf3c41d475382eeb.tar.gz sail-riscv-c18905486156fe245ba4edbddf3c41d475382eeb.tar.bz2 |
Re-import tests from sail repo.
Diffstat (limited to 'test/tests/disabled')
-rw-r--r-- | test/tests/disabled/rv64mi-p-access.elf | bin | 0 -> 9296 bytes | |||
-rw-r--r-- | test/tests/disabled/rv64mi-p-sbreak.dump | 130 | ||||
-rw-r--r-- | test/tests/disabled/rv64mi-p-sbreak.elf | bin | 0 -> 9328 bytes | |||
-rw-r--r-- | test/tests/disabled/rv64si-p-sbreak.dump | 128 | ||||
-rw-r--r-- | test/tests/disabled/rv64si-p-sbreak.elf | bin | 0 -> 9328 bytes | |||
-rw-r--r-- | test/tests/disabled/rv64ua-p-lrsc.dump | 178 | ||||
-rw-r--r-- | test/tests/disabled/rv64ua-p-lrsc.elf | bin | 0 -> 14632 bytes | |||
-rw-r--r-- | test/tests/disabled/rv64ua-v-lrsc.elf | bin | 0 -> 19816 bytes |
8 files changed, 436 insertions, 0 deletions
diff --git a/test/tests/disabled/rv64mi-p-access.elf b/test/tests/disabled/rv64mi-p-access.elf Binary files differnew file mode 100644 index 0000000..9bd96fb --- /dev/null +++ b/test/tests/disabled/rv64mi-p-access.elf diff --git a/test/tests/disabled/rv64mi-p-sbreak.dump b/test/tests/disabled/rv64mi-p-sbreak.dump new file mode 100644 index 0000000..8e03511 --- /dev/null +++ b/test/tests/disabled/rv64mi-p-sbreak.dump @@ -0,0 +1,130 @@ + +rv64mi-p-sbreak: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 00000f17 auipc t5,0x0 + 80000024: 118f0f13 addi t5,t5,280 # 80000138 <mtvec_handler> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00002537 lui a0,0x2 + 800000ec: 8005051b addiw a0,a0,-2048 + 800000f0: 30052073 csrs mstatus,a0 + 800000f4: 00000297 auipc t0,0x0 + 800000f8: 01428293 addi t0,t0,20 # 80000108 <reset_vector+0xbc> + 800000fc: 34129073 csrw mepc,t0 + 80000100: f1402573 csrr a0,mhartid + 80000104: 30200073 mret + 80000108: 00200193 li gp,2 + +000000008000010c <do_break>: + 8000010c: 00100073 ebreak + 80000110: 0080006f j 80000118 <fail> + 80000114: 00301c63 bne zero,gp,8000012c <pass> + +0000000080000118 <fail>: + 80000118: 0ff0000f fence + 8000011c: 00018063 beqz gp,8000011c <fail+0x4> + 80000120: 00119193 slli gp,gp,0x1 + 80000124: 0011e193 ori gp,gp,1 + 80000128: 00000073 ecall + +000000008000012c <pass>: + 8000012c: 0ff0000f fence + 80000130: 00100193 li gp,1 + 80000134: 00000073 ecall + +0000000080000138 <mtvec_handler>: + 80000138: 00300313 li t1,3 + 8000013c: 342022f3 csrr t0,mcause + 80000140: fc629ce3 bne t0,t1,80000118 <fail> + 80000144: 00000317 auipc t1,0x0 + 80000148: fc830313 addi t1,t1,-56 # 8000010c <do_break> + 8000014c: 341022f3 csrr t0,mepc + 80000150: fc6294e3 bne t0,t1,80000118 <fail> + 80000154: fd9ff06f j 8000012c <pass> + 80000158: c0001073 unimp + 8000015c: 0000 unimp + 8000015e: 0000 unimp + 80000160: 0000 unimp + 80000162: 0000 unimp + 80000164: 0000 unimp + 80000166: 0000 unimp + 80000168: 0000 unimp + 8000016a: 0000 unimp + 8000016c: 0000 unimp + 8000016e: 0000 unimp + 80000170: 0000 unimp + 80000172: 0000 unimp + 80000174: 0000 unimp + 80000176: 0000 unimp + 80000178: 0000 unimp + 8000017a: 0000 unimp + 8000017c: 0000 unimp + 8000017e: 0000 unimp + 80000180: 0000 unimp + 80000182: 0000 unimp diff --git a/test/tests/disabled/rv64mi-p-sbreak.elf b/test/tests/disabled/rv64mi-p-sbreak.elf Binary files differnew file mode 100644 index 0000000..0319c2d --- /dev/null +++ b/test/tests/disabled/rv64mi-p-sbreak.elf diff --git a/test/tests/disabled/rv64si-p-sbreak.dump b/test/tests/disabled/rv64si-p-sbreak.dump new file mode 100644 index 0000000..e981c54 --- /dev/null +++ b/test/tests/disabled/rv64si-p-sbreak.dump @@ -0,0 +1,128 @@ + +rv64si-p-sbreak: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 00000297 auipc t0,0x0 + 800000c4: 08028293 addi t0,t0,128 # 80000140 <stvec_handler> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00001537 lui a0,0x1 + 800000ec: 8005051b addiw a0,a0,-2048 + 800000f0: 30052073 csrs mstatus,a0 + 800000f4: 02200513 li a0,34 + 800000f8: 30352073 csrs mideleg,a0 + 800000fc: 00000297 auipc t0,0x0 + 80000100: 01428293 addi t0,t0,20 # 80000110 <reset_vector+0xc4> + 80000104: 34129073 csrw mepc,t0 + 80000108: f1402573 csrr a0,mhartid + 8000010c: 30200073 mret + 80000110: 00200193 li gp,2 + +0000000080000114 <do_break>: + 80000114: 00100073 ebreak + 80000118: 0080006f j 80000120 <fail> + 8000011c: 00301c63 bne zero,gp,80000134 <pass> + +0000000080000120 <fail>: + 80000120: 0ff0000f fence + 80000124: 00018063 beqz gp,80000124 <fail+0x4> + 80000128: 00119193 slli gp,gp,0x1 + 8000012c: 0011e193 ori gp,gp,1 + 80000130: 00000073 ecall + +0000000080000134 <pass>: + 80000134: 0ff0000f fence + 80000138: 00100193 li gp,1 + 8000013c: 00000073 ecall + +0000000080000140 <stvec_handler>: + 80000140: 00300313 li t1,3 + 80000144: 142022f3 csrr t0,scause + 80000148: fc629ce3 bne t0,t1,80000120 <fail> + 8000014c: 00000317 auipc t1,0x0 + 80000150: fc830313 addi t1,t1,-56 # 80000114 <do_break> + 80000154: 141022f3 csrr t0,sepc + 80000158: fc6294e3 bne t0,t1,80000120 <fail> + 8000015c: fd9ff06f j 80000134 <pass> + 80000160: c0001073 unimp + 80000164: 0000 unimp + 80000166: 0000 unimp + 80000168: 0000 unimp + 8000016a: 0000 unimp + 8000016c: 0000 unimp + 8000016e: 0000 unimp + 80000170: 0000 unimp + 80000172: 0000 unimp + 80000174: 0000 unimp + 80000176: 0000 unimp + 80000178: 0000 unimp + 8000017a: 0000 unimp + 8000017c: 0000 unimp + 8000017e: 0000 unimp + 80000180: 0000 unimp + 80000182: 0000 unimp diff --git a/test/tests/disabled/rv64si-p-sbreak.elf b/test/tests/disabled/rv64si-p-sbreak.elf Binary files differnew file mode 100644 index 0000000..2d6c2e7 --- /dev/null +++ b/test/tests/disabled/rv64si-p-sbreak.elf diff --git a/test/tests/disabled/rv64ua-p-lrsc.dump b/test/tests/disabled/rv64ua-p-lrsc.dump new file mode 100644 index 0000000..4aec511 --- /dev/null +++ b/test/tests/disabled/rv64ua-p-lrsc.dump @@ -0,0 +1,178 @@ + +rv64ua-p-lrsc: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <reset_vector+0xb0> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + 800000fc: 00002517 auipc a0,0x2 + 80000100: f0450513 addi a0,a0,-252 # 80002000 <begin_signature> + 80000104: 00100593 li a1,1 + 80000108: 00b5262f amoadd.w a2,a1,(a0) + 8000010c: 00100693 li a3,1 + 80000110: fed67ee3 bleu a3,a2,8000010c <reset_vector+0xc0> + 80000114: 00052583 lw a1,0(a0) + 80000118: fed5eee3 bltu a1,a3,80000114 <reset_vector+0xc8> + +000000008000011c <test_2>: + 8000011c: 00002517 auipc a0,0x2 + 80000120: eec50513 addi a0,a0,-276 # 80002008 <foo> + 80000124: 1805272f sc.w a4,zero,(a0) + 80000128: 00100e93 li t4,1 + 8000012c: 00200193 li gp,2 + 80000130: 09d71863 bne a4,t4,800001c0 <fail> + +0000000080000134 <test_3>: + 80000134: 00002517 auipc a0,0x2 + 80000138: ed450513 addi a0,a0,-300 # 80002008 <foo> + 8000013c: 40050593 addi a1,a0,1024 + 80000140: 1005a5af lr.w a1,(a1) + 80000144: 18b5272f sc.w a4,a1,(a0) + 80000148: 00100e93 li t4,1 + 8000014c: 00300193 li gp,3 + 80000150: 07d71863 bne a4,t4,800001c0 <fail> + 80000154: 00002517 auipc a0,0x2 + 80000158: eb450513 addi a0,a0,-332 # 80002008 <foo> + 8000015c: 40000593 li a1,1024 + 80000160: 00160613 addi a2,a2,1 + 80000164: 1005272f lr.w a4,(a0) + 80000168: 00c70733 add a4,a4,a2 + 8000016c: 18e5272f sc.w a4,a4,(a0) + 80000170: fe071ae3 bnez a4,80000164 <test_3+0x30> + 80000174: fff58593 addi a1,a1,-1 + 80000178: fe0596e3 bnez a1,80000164 <test_3+0x30> + 8000017c: 00002517 auipc a0,0x2 + 80000180: e8850513 addi a0,a0,-376 # 80002004 <barrier> + 80000184: 00100593 li a1,1 + 80000188: 00b5202f amoadd.w zero,a1,(a0) + 8000018c: 00052583 lw a1,0(a0) + 80000190: fed5cee3 blt a1,a3,8000018c <test_3+0x58> + 80000194: 0ff0000f fence + +0000000080000198 <test_4>: + 80000198: 00002517 auipc a0,0x2 + 8000019c: e7052503 lw a0,-400(a0) # 80002008 <foo> + 800001a0: 00969593 slli a1,a3,0x9 + 800001a4: 40b50533 sub a0,a0,a1 + 800001a8: fff68693 addi a3,a3,-1 + 800001ac: fe06dce3 bgez a3,800001a4 <test_4+0xc> + 800001b0: 00000e93 li t4,0 + 800001b4: 00400193 li gp,4 + 800001b8: 01d51463 bne a0,t4,800001c0 <fail> + 800001bc: 00301c63 bne zero,gp,800001d4 <pass> + +00000000800001c0 <fail>: + 800001c0: 0ff0000f fence + 800001c4: 00018063 beqz gp,800001c4 <fail+0x4> + 800001c8: 00119193 slli gp,gp,0x1 + 800001cc: 0011e193 ori gp,gp,1 + 800001d0: 00000073 ecall + +00000000800001d4 <pass>: + 800001d4: 0ff0000f fence + 800001d8: 00100193 li gp,1 + 800001dc: 00000073 ecall + 800001e0: c0001073 unimp + 800001e4: 0000 unimp + 800001e6: 0000 unimp + 800001e8: 0000 unimp + 800001ea: 0000 unimp + 800001ec: 0000 unimp + 800001ee: 0000 unimp + 800001f0: 0000 unimp + 800001f2: 0000 unimp + 800001f4: 0000 unimp + 800001f6: 0000 unimp + 800001f8: 0000 unimp + 800001fa: 0000 unimp + 800001fc: 0000 unimp + 800001fe: 0000 unimp + 80000200: 0000 unimp + 80000202: 0000 unimp + +Disassembly of section .data: + +0000000080002000 <begin_signature>: + 80002000: 0000 unimp + 80002002: 0000 unimp + +0000000080002004 <barrier>: + 80002004: 0000 unimp + 80002006: 0000 unimp + +0000000080002008 <foo>: + 80002008: 0000 unimp + 8000200a: 0000 unimp + 8000200c: 0000 unimp + 8000200e: 0000 unimp diff --git a/test/tests/disabled/rv64ua-p-lrsc.elf b/test/tests/disabled/rv64ua-p-lrsc.elf Binary files differnew file mode 100644 index 0000000..bff6664 --- /dev/null +++ b/test/tests/disabled/rv64ua-p-lrsc.elf diff --git a/test/tests/disabled/rv64ua-v-lrsc.elf b/test/tests/disabled/rv64ua-v-lrsc.elf Binary files differnew file mode 100644 index 0000000..10a2866 --- /dev/null +++ b/test/tests/disabled/rv64ua-v-lrsc.elf |