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author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2018-10-06 19:42:22 -0700 |
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committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2018-10-23 15:32:15 -0700 |
commit | eb9e2982732247c95a8501291ff56638eb2ae19c (patch) | |
tree | 3797fad37b37aa4930dd73ecdf32b4085e0e2b4c /riscv_sys.sail | |
parent | 1d78e6c76df8fa1cdf961f208035bab849ad11f8 (diff) | |
download | sail-riscv-eb9e2982732247c95a8501291ff56638eb2ae19c.zip sail-riscv-eb9e2982732247c95a8501291ff56638eb2ae19c.tar.gz sail-riscv-eb9e2982732247c95a8501291ff56638eb2ae19c.tar.bz2 |
RISC-V: fix: sstatus.SD depends on .XS and .FS.
Diffstat (limited to 'riscv_sys.sail')
-rw-r--r-- | riscv_sys.sail | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/riscv_sys.sail b/riscv_sys.sail index 59bff60..37c4511 100644 --- a/riscv_sys.sail +++ b/riscv_sys.sail @@ -375,13 +375,17 @@ function lower_mstatus(m : Mstatus) -> Sstatus = { } function lift_sstatus(m : Mstatus, s : Sstatus) -> Mstatus = { - let m = update_SD(m, s.SD()); // FIXME: This should be parameterized by a platform setting. For now, match spike. // let m = update_UXL(m, s.UXL()); let m = update_MXR(m, s.MXR()); let m = update_SUM(m, s.SUM()); + + // FIXME: Should XS and FS check whether X and F|D are supported in misa? let m = update_XS(m, s.XS()); let m = update_FS(m, s.FS()); + let m = update_SD(m, extStatus_of_bits(m.FS()) == Dirty + | extStatus_of_bits(m.XS()) == Dirty); + let m = update_SPP(m, s.SPP()); let m = update_SPIE(m, s.SPIE()); let m = update_UPIE(m, s.UPIE()); |