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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2018-06-07 16:44:59 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2018-06-07 16:44:59 -0700 |
| commit | 9ac11ad7a2316acf41654a9d48d117f6f1b02397 (patch) | |
| tree | 83c24e477282b1359f72a7b31e037ffad5d2074f /riscv_mem.sail | |
| parent | 62b3c1cd55dc9c83367a2f3e1a664127e0e4f354 (diff) | |
| download | sail-riscv-9ac11ad7a2316acf41654a9d48d117f6f1b02397.zip sail-riscv-9ac11ad7a2316acf41654a9d48d117f6f1b02397.tar.gz sail-riscv-9ac11ad7a2316acf41654a9d48d117f6f1b02397.tar.bz2 | |
Fix width guards on htif accesses.
Diffstat (limited to 'riscv_mem.sail')
| -rw-r--r-- | riscv_mem.sail | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/riscv_mem.sail b/riscv_mem.sail index 0fc9ddb..0cfc3db 100644 --- a/riscv_mem.sail +++ b/riscv_mem.sail @@ -20,10 +20,8 @@ function checked_mem_read(t : ReadType, addr : xlenbits, width : atom('n)) -> fo else if t == Data then { if within_clint(addr, width) then clint_load(addr, width) - /* todo: handle constraint on 'n - else if within_htif_readable(addr, width) + else if within_htif_readable(addr, width) & (1 <= 'n) then htif_load(addr, width) - */ else MemException(E_Load_Access_Fault) } else MemException(E_Load_Access_Fault) @@ -105,7 +103,7 @@ function checked_mem_write(addr : xlenbits, width : atom('n), data: bits(8 * 'n) then phys_mem_write(addr, width, data) else if within_clint(addr, width) then clint_store(addr, width, data) - else if within_htif_writable(addr, width) & sizeof('n) <= 8 // FIXME + else if within_htif_writable(addr, width) & 'n <= 8 then htif_store(addr, width, data) else MemException(E_SAMO_Access_Fault) |