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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2018-05-18 17:54:02 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2018-05-21 18:00:03 -0700 |
| commit | 61d0eb465740c6dd350bab8536e839a3aaf2f715 (patch) | |
| tree | b53652612a10fde454af9c8ae2055937af5c337c /riscv_mem.sail | |
| parent | d4a5a980a7fe67262c0c11e8f82450de09c2f28d (diff) | |
| download | sail-riscv-61d0eb465740c6dd350bab8536e839a3aaf2f715.zip sail-riscv-61d0eb465740c6dd350bab8536e839a3aaf2f715.tar.gz sail-riscv-61d0eb465740c6dd350bab8536e839a3aaf2f715.tar.bz2 | |
Move mem-op-result to _sys to be usable from _platform.
Diffstat (limited to 'riscv_mem.sail')
| -rw-r--r-- | riscv_mem.sail | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/riscv_mem.sail b/riscv_mem.sail index 375f48b..10fd98f 100644 --- a/riscv_mem.sail +++ b/riscv_mem.sail @@ -1,10 +1,5 @@ /* memory */ -union MemoryOpResult ('a : Type) = { - MemValue : 'a, - MemException: ExceptionType -} - function is_aligned_addr (addr : xlenbits, width : atom('n)) -> forall 'n. bool = unsigned(addr) % width == 0 |