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authorPrashanth Mundkur <prashanth.mundkur@gmail.com>2019-03-07 10:24:51 -0800
committerPrashanth Mundkur <prashanth.mundkur@gmail.com>2019-03-07 10:24:51 -0800
commite1161737970dace76354c5d83e43947e714dbf34 (patch)
tree6d9039d08a5e052dda50df27ce836f9da964fbd2 /os-boot/rv64-64mb.dts
parent6e69bfb8a93741bdd6ecf7af815e8ed32726d2cd (diff)
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Diffstat (limited to 'os-boot/rv64-64mb.dts')
-rw-r--r--os-boot/rv64-64mb.dts45
1 files changed, 45 insertions, 0 deletions
diff --git a/os-boot/rv64-64mb.dts b/os-boot/rv64-64mb.dts
new file mode 100644
index 0000000..84969e4
--- /dev/null
+++ b/os-boot/rv64-64mb.dts
@@ -0,0 +1,45 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "ucbbar,spike-bare-dev";
+ model = "ucbbar,spike-bare";
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <10000000>;
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64imac";
+ mmu-type = "riscv,sv39";
+ clock-frequency = <1000000000>;
+ CPU0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ };
+ };
+ };
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x4000000>;
+ };
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "ucbbar,spike-bare-soc", "simple-bus";
+ ranges;
+ clint@2000000 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7 >;
+ reg = <0x0 0x2000000 0x0 0xc0000>;
+ };
+ };
+ htif {
+ compatible = "ucb,htif0";
+ };
+};