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author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-03-07 12:48:58 -0800 |
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committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-03-07 14:48:57 -0800 |
commit | 1d85b196527dfeb1e126364afeaa5b7e632cc2a9 (patch) | |
tree | bf91691b93f87298f2e41cd908956027396f8946 /os-boot/rv64-2gb.dts | |
parent | 7e6961b52183158d8d22344fa509b03253e04463 (diff) | |
download | sail-riscv-1d85b196527dfeb1e126364afeaa5b7e632cc2a9.zip sail-riscv-1d85b196527dfeb1e126364afeaa5b7e632cc2a9.tar.gz sail-riscv-1d85b196527dfeb1e126364afeaa5b7e632cc2a9.tar.bz2 |
Fix docs about sel4 boot.
Diffstat (limited to 'os-boot/rv64-2gb.dts')
-rw-r--r-- | os-boot/rv64-2gb.dts | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/os-boot/rv64-2gb.dts b/os-boot/rv64-2gb.dts new file mode 100644 index 0000000..4cbb2d4 --- /dev/null +++ b/os-boot/rv64-2gb.dts @@ -0,0 +1,45 @@ +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "ucbbar,spike-bare-dev"; + model = "ucbbar,spike-bare"; + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <10000000>; + CPU0: cpu@0 { + device_type = "cpu"; + reg = <0>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imac"; + mmu-type = "riscv,sv39"; + clock-frequency = <1000000000>; + CPU0_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "ucbbar,spike-bare-soc", "simple-bus"; + ranges; + clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7 >; + reg = <0x0 0x2000000 0x0 0xc0000>; + }; + }; + htif { + compatible = "ucb,htif0"; + }; +}; |