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| author | Tim Hutt <timothy.hutt@codasip.com> | 2023-10-10 12:41:22 +0100 |
|---|---|---|
| committer | Bill McSpadden <bill@riscv.org> | 2024-02-05 08:48:04 -0600 |
| commit | d5e89a71e3a84495c1b88a7749c25fd6b9da684b (patch) | |
| tree | b1898a8a1083ae49e6dcdc45327dedb1d91da758 /model/riscv_vmem_sv32.sail | |
| parent | 23f18200b771174e601fb58e7a857291fb32d063 (diff) | |
| download | sail-riscv-d5e89a71e3a84495c1b88a7749c25fd6b9da684b.zip sail-riscv-d5e89a71e3a84495c1b88a7749c25fd6b9da684b.tar.gz sail-riscv-d5e89a71e3a84495c1b88a7749c25fd6b9da684b.tar.bz2 | |
Rename string_of_int to dec_str
And string_of_bits to bits_str. These are the names that Sail uses so it makes sense to use them.
Diffstat (limited to 'model/riscv_vmem_sv32.sail')
| -rw-r--r-- | model/riscv_vmem_sv32.sail | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/model/riscv_vmem_sv32.sail b/model/riscv_vmem_sv32.sail index 3b3ce1c..15e8ef2 100644 --- a/model/riscv_vmem_sv32.sail +++ b/model/riscv_vmem_sv32.sail @@ -84,7 +84,7 @@ function walk32(vaddr, ac, priv, mxr, do_sum, ptb, level, global, ext_ptw) = { let pte_addr = ptb + pt_ofs; match (mem_read_priv(Read(Data), Supervisor, to_phys_addr(pte_addr), 4, false, false, false)) { MemException(_) => { -/* print("walk32(vaddr=" ^ BitStr(vaddr) ^ " level=" ^ string_of_int(level) +/* print("walk32(vaddr=" ^ BitStr(vaddr) ^ " level=" ^ dec_str(level) ^ " pt_base=" ^ BitStr(to_phys_addr(ptb)) ^ " pt_ofs=" ^ BitStr(to_phys_addr(pt_ofs)) ^ " pte_addr=" ^ BitStr(to_phys_addr(pte_addr)) @@ -97,7 +97,7 @@ function walk32(vaddr, ac, priv, mxr, do_sum, ptb, level, global, ext_ptw) = { let ext_pte : extPte = default_sv32_ext_pte; let pattr = Mk_PTE_Bits(pbits); let is_global = global | (pattr[G] == 0b1); -/* print("walk32(vaddr=" ^ BitStr(vaddr) ^ " level=" ^ string_of_int(level) +/* print("walk32(vaddr=" ^ BitStr(vaddr) ^ " level=" ^ dec_str(level) ^ " pt_base=" ^ BitStr(to_phys_addr(ptb)) ^ " pt_ofs=" ^ BitStr(to_phys_addr(pt_ofs)) ^ " pte_addr=" ^ BitStr(to_phys_addr(pte_addr)) |