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| author | Alexander Richardson <alexrichardson@google.com> | 2023-03-14 12:26:10 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-03-14 07:26:10 -0500 |
| commit | 78521ce0811e48e87f387cfa6a705088dabfaf86 (patch) | |
| tree | 2c5711507f46b69359ca9b34f515af7b96306668 /model/riscv_vmem_sv32.sail | |
| parent | 6df1e784cf80e909cf7d8ec77f139805c2730e08 (diff) | |
| download | sail-riscv-78521ce0811e48e87f387cfa6a705088dabfaf86.zip sail-riscv-78521ce0811e48e87f387cfa6a705088dabfaf86.tar.gz sail-riscv-78521ce0811e48e87f387cfa6a705088dabfaf86.tar.bz2 | |
Use not() instead of ~() for boolean negation (#210)
This may be more readable and also matches the sail-cheri-riscv model.
For now this keeps ~ overloaded to accept bool, but in the future we may
want to consider removing it (which is what I did to find all uses
modified in this patch)
Diffstat (limited to 'model/riscv_vmem_sv32.sail')
| -rw-r--r-- | model/riscv_vmem_sv32.sail | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/model/riscv_vmem_sv32.sail b/model/riscv_vmem_sv32.sail index 2b17844..d2e86e3 100644 --- a/model/riscv_vmem_sv32.sail +++ b/model/riscv_vmem_sv32.sail @@ -197,7 +197,7 @@ function translate32(asid, ptb, vAddr, ac, priv, mxr, do_sum, level, ext_ptw) = match update_PTE_Bits(pteBits, ac, ext_pte) { None() => TR_Address(ent.pAddr | EXTZ(vAddr & ent.vAddrMask), ext_ptw), Some(pbits, ext) => { - if ~ (plat_enable_dirty_update ()) + if not(plat_enable_dirty_update()) then { /* pte needs dirty/accessed update but that is not enabled */ TR_Failure(PTW_PTE_Update(), ext_ptw) @@ -230,7 +230,7 @@ function translate32(asid, ptb, vAddr, ac, priv, mxr, do_sum, level, ext_ptw) = TR_Address(pAddr, ext_ptw) }, Some(pbits, ext) => - if ~ (plat_enable_dirty_update ()) + if not(plat_enable_dirty_update()) then { /* pte needs dirty/accessed update but that is not enabled */ TR_Failure(PTW_PTE_Update(), ext_ptw) |