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authorAlasdair Armstrong <alasdair.armstrong@cl.cam.ac.uk>2019-08-19 18:49:23 +0100
committerAlasdair Armstrong <alasdair.armstrong@cl.cam.ac.uk>2019-08-19 18:53:00 +0100
commita381a832bb39bb7571725f75c27dc257762cd693 (patch)
tree29c1d4210ffa91e372f94f2567e3f3275b466b4e /model/riscv_vmem_rv64.sail
parentc0c70effa02100c16870251b2a27b79a1cab7331 (diff)
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RISC-V spec, without implicit casts
Diffstat (limited to 'model/riscv_vmem_rv64.sail')
-rw-r--r--model/riscv_vmem_rv64.sail6
1 files changed, 3 insertions, 3 deletions
diff --git a/model/riscv_vmem_rv64.sail b/model/riscv_vmem_rv64.sail
index e3cca0b..3153983 100644
--- a/model/riscv_vmem_rv64.sail
+++ b/model/riscv_vmem_rv64.sail
@@ -24,7 +24,7 @@ function translationMode(priv) = {
},
Some(RV32) => {
let s = Mk_Satp32(satp[31..0]);
- if s.Mode() == false then Sbare else Sv32
+ if s.Mode() == 0b0 then Sbare else Sv32
},
_ => internal_error("unsupported address translation arch")
}
@@ -39,8 +39,8 @@ function translateAddr(vAddr, ac) = {
Execute => cur_privilege,
_ => effectivePrivilege(mstatus, cur_privilege)
};
- let mxr : bool = mstatus.MXR() == true;
- let do_sum : bool = mstatus.SUM() == true;
+ let mxr : bool = mstatus.MXR() == 0b1;
+ let do_sum : bool = mstatus.SUM() == 0b1;
let mode : SATPMode = translationMode(effPriv);
let asid = curAsid64(satp);