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| author | Scott Johnson <scott.johnson@arilinc.com> | 2020-04-21 18:50:34 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-21 18:50:34 -0700 |
| commit | 38f52c99289e31aef72a4272e1a46b7a3398e076 (patch) | |
| tree | 263504e8791171e3b241bd2971f7a5716c2f06ab /model/riscv_vmem_rv64.sail | |
| parent | 7be062b12c1b581253bc63ef223266c32c9eeddc (diff) | |
| download | sail-riscv-38f52c99289e31aef72a4272e1a46b7a3398e076.zip sail-riscv-38f52c99289e31aef72a4272e1a46b7a3398e076.tar.gz sail-riscv-38f52c99289e31aef72a4272e1a46b7a3398e076.tar.bz2 | |
Fix mstatus.MPRV fetches (#48)
* Add {} so I can add a new variable here next
* Create new variable which I will soon reuse
* Plumb in the access type to effectivePrivilege
So I can use it to fix #47 next.
* Instruction fetches should not be affected by mstatus.MPRV
Fixes #47.
* Remove now-redundant privilege calculation
Diffstat (limited to 'model/riscv_vmem_rv64.sail')
| -rw-r--r-- | model/riscv_vmem_rv64.sail | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/model/riscv_vmem_rv64.sail b/model/riscv_vmem_rv64.sail index 8b7dc44..8abd68e 100644 --- a/model/riscv_vmem_rv64.sail +++ b/model/riscv_vmem_rv64.sail @@ -35,10 +35,7 @@ function translationMode(priv) = { val translateAddr : (xlenbits, AccessType(ext_access_type)) -> TR_Result(xlenbits, ExceptionType) effect {escape, rmem, rmemt, rreg, wmv, wmvt, wreg} function translateAddr(vAddr, ac) = { - let effPriv : Privilege = match ac { - Execute() => cur_privilege, - _ => effectivePrivilege(mstatus, cur_privilege) - }; + let effPriv : Privilege = effectivePrivilege(ac, mstatus, cur_privilege); let mxr : bool = mstatus.MXR() == 0b1; let do_sum : bool = mstatus.SUM() == 0b1; let mode : SATPMode = translationMode(effPriv); |