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| author | Alasdair <alasdair.armstrong@cl.cam.ac.uk> | 2023-11-18 00:16:49 +0000 |
|---|---|---|
| committer | Bill McSpadden <bill@riscv.org> | 2023-12-19 12:51:23 -0800 |
| commit | d7a3d8012fd579f40e53a29569141d72dd5e0c32 (patch) | |
| tree | 345e69128d025d0ebcf3a598bde638606e25066b /model/riscv_vext_regs.sail | |
| parent | 6beb7c242549cbcb20ab28969705d99922a33a97 (diff) | |
| download | sail-riscv-d7a3d8012fd579f40e53a29569141d72dd5e0c32.zip sail-riscv-d7a3d8012fd579f40e53a29569141d72dd5e0c32.tar.gz sail-riscv-d7a3d8012fd579f40e53a29569141d72dd5e0c32.tar.bz2 | |
lem: Fix issues created by vector extension
Switch to bitlist representation because the machine words
can't handle the vector code currently
Remove RMEM target from default set of targets in Makefile.
This is only interesting for RMEM maintainers. There's no reason for it
to be generated by default, and it's also broken.
While we are hacking on these files purge the duplicate versions for Sail 0.11+
Diffstat (limited to 'model/riscv_vext_regs.sail')
0 files changed, 0 insertions, 0 deletions