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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-19 15:49:56 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-19 15:49:56 -0800 |
| commit | 6a4eb9211bab5070dc55cea9046e1ffc4e20eafc (patch) | |
| tree | 2c9f667f8852a89f66896bbb62b4c09deceea034 /model/riscv_sys_control.sail | |
| parent | a238acdcd83f2db3c6d549775f16ac8b4ad2291e (diff) | |
| download | sail-riscv-6a4eb9211bab5070dc55cea9046e1ffc4e20eafc.zip sail-riscv-6a4eb9211bab5070dc55cea9046e1ffc4e20eafc.tar.gz sail-riscv-6a4eb9211bab5070dc55cea9046e1ffc4e20eafc.tar.bz2 | |
Use sizeof xlen instead of the value definitions of xlen.
Diffstat (limited to 'model/riscv_sys_control.sail')
| -rw-r--r-- | model/riscv_sys_control.sail | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail index 5238066..8a0e1cf 100644 --- a/model/riscv_sys_control.sail +++ b/model/riscv_sys_control.sail @@ -36,8 +36,8 @@ function is_CSR_defined (csr : bits(12), p : Privilege) -> bool = 0xB00 => p == Machine, // mcycle 0xB02 => p == Machine, // minstret - 0xB80 => p == Machine & (xlen == 32), // mcycleh - 0xB82 => p == Machine & (xlen == 32), // minstreth + 0xB80 => p == Machine & (sizeof(xlen) == 32), // mcycleh + 0xB82 => p == Machine & (sizeof(xlen) == 32), // minstreth /* disabled trigger/debug module */ 0x7a0 => p == Machine, @@ -65,9 +65,9 @@ function is_CSR_defined (csr : bits(12), p : Privilege) -> bool = 0xC01 => p == User, // time 0xC02 => p == User, // instret - 0xC80 => p == User & (xlen == 32), // cycleh - 0xC81 => p == User & (xlen == 32), // timeh - 0xC82 => p == User & (xlen == 32), // instreth + 0xC80 => p == User & (sizeof(xlen) == 32), // cycleh + 0xC81 => p == User & (sizeof(xlen) == 32), // timeh + 0xC82 => p == User & (sizeof(xlen) == 32), // instreth /* check extensions */ _ => is_UExt_CSR_defined(csr, p) // 'N' extension |