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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-05-01 19:21:24 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-05-02 09:08:36 -0700 |
| commit | e70db368638162b41a924c3b5c7df7531559af70 (patch) | |
| tree | b6dd79518daa65a2e12be7ae3c9399342a4fd466 /model/riscv_step.sail | |
| parent | 8d53d096103a6f66b58e3f9707d64b6348c569e1 (diff) | |
| download | sail-riscv-e70db368638162b41a924c3b5c7df7531559af70.zip sail-riscv-e70db368638162b41a924c3b5c7df7531559af70.tar.gz sail-riscv-e70db368638162b41a924c3b5c7df7531559af70.tar.bz2 | |
rvfi: initialize registers between test runs.
Diffstat (limited to 'model/riscv_step.sail')
| -rw-r--r-- | model/riscv_step.sail | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/model/riscv_step.sail b/model/riscv_step.sail index fda2777..c6b7fc1 100644 --- a/model/riscv_step.sail +++ b/model/riscv_step.sail @@ -93,5 +93,6 @@ function init_model () -> unit = { init_vmem (); /* virtual memory */ /* initialize extensions last */ + ext_init (); ext_init_regs (); } |