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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2020-04-01 09:06:20 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2020-04-01 09:06:20 -0700 |
| commit | d1fe5f8f418275cc8119866a2f3827fe5dc102e4 (patch) | |
| tree | 6ad3a46145a5a2c4a375c47ba905bf5b5f55254d /model/riscv_pmp_regs.sail | |
| parent | 695d8e56cf9d4f1b6153f22be5bb046026b00287 (diff) | |
| download | sail-riscv-d1fe5f8f418275cc8119866a2f3827fe5dc102e4.zip sail-riscv-d1fe5f8f418275cc8119866a2f3827fe5dc102e4.tar.gz sail-riscv-d1fe5f8f418275cc8119866a2f3827fe5dc102e4.tar.bz2 | |
Add a clarifying comment.
Diffstat (limited to 'model/riscv_pmp_regs.sail')
| -rw-r--r-- | model/riscv_pmp_regs.sail | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/model/riscv_pmp_regs.sail b/model/riscv_pmp_regs.sail index f51ab8b..30231b8 100644 --- a/model/riscv_pmp_regs.sail +++ b/model/riscv_pmp_regs.sail @@ -93,7 +93,8 @@ function pmpTORLocked(cfg: Pmpcfg_ent) -> bool = (cfg.L() == 0b1) & (pmpAddrMatchType_of_bits(cfg.A()) == TOR) function pmpWriteCfg(cfg: Pmpcfg_ent, v: bits(8)) -> Pmpcfg_ent = - if pmpLocked(cfg) then cfg else Mk_Pmpcfg_ent(v & 0x9f) // 0x9f masks reserved bits. + if pmpLocked(cfg) then cfg + else Mk_Pmpcfg_ent(v & 0x9f) // Bits 5 and 6 are zero. val pmpWriteCfgReg : forall 'n, 0 <= 'n < 4 . (atom('n), xlenbits) -> unit effect {rreg, wreg} function pmpWriteCfgReg(n, v) = { |