Update bitfield syntax

1 files changed, 3 insertions, 3 deletions

diff --git a/model/riscv_pmp_regs.sail b/model/riscv_pmp_regs.sail
index a9e4676..65afd2b 100644
--- a/model/riscv_pmp_regs.sail
+++ b/model/riscv_pmp_regs.sail
@@ -68,7 +68,7 @@ function pmpReadCfgReg(n : range(0, 15)) -> xlenbits = {
 
 function pmpReadAddrReg(n : range(0, 63)) -> xlenbits = {
   let G = sys_pmp_grain();
-  let match_type = pmpcfg_n[n].A();
+  let match_type = pmpcfg_n[n][A];
   let addr = pmpaddr_n[n];
 
   match match_type[1] {
@@ -104,12 +104,12 @@ function pmpWriteCfg(n: range(0, 63), cfg: Pmpcfg_ent, v: bits(8)) -> Pmpcfg_ent
     // "The R, W, and X fields form a collective WARL field for which the combinations with R=0 and W=1 are reserved."
     // In this implementation if R=0 and W=1 then R, W and X are all set to 0.
     // This is the least risky option from a security perspective.
-    let cfg = if cfg.W() == 0b1 & cfg.R() == 0b0 then [cfg with X = 0b0, W = 0b0, R = 0b0] else cfg;
+    let cfg = if cfg[W] == 0b1 & cfg[R] == 0b0 then [cfg with X = 0b0, W = 0b0, R = 0b0] else cfg;
 
     // "When G >= 1, the NA4 mode is not selectable."
     // In this implementation we set it to OFF if NA4 is selected.
     // This is the least risky option from a security perspective.
-    let cfg = if sys_pmp_grain() >= 1 & pmpAddrMatchType_of_bits(cfg.A()) == NA4
+    let cfg = if sys_pmp_grain() >= 1 & pmpAddrMatchType_of_bits(cfg[A]) == NA4
               then [cfg with A = pmpAddrMatchType_to_bits(OFF)]
               else cfg;