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| author | Alasdair <alasdair.armstrong@cl.cam.ac.uk> | 2023-06-29 13:30:11 +0100 |
|---|---|---|
| committer | Bill McSpadden <bill@riscv.org> | 2023-08-01 08:54:15 -0500 |
| commit | 58cac61d9ddde591902c933a9dfa5d8ba3fca6da (patch) | |
| tree | 68b5d44c3008a16af32be9c0e099d8ef1fa39ad5 /model/riscv_pmp_regs.sail | |
| parent | ae905fb888cbb21c782bacf86be182d9e20b8895 (diff) | |
| download | sail-riscv-58cac61d9ddde591902c933a9dfa5d8ba3fca6da.zip sail-riscv-58cac61d9ddde591902c933a9dfa5d8ba3fca6da.tar.gz sail-riscv-58cac61d9ddde591902c933a9dfa5d8ba3fca6da.tar.bz2 | |
Rename EXTZ and EXTS
Rename EXTZ to zero_extend and EXTS to sign_extend. Two main reasons
for doing this - it means that the source more closely follows the
descriptions in the documentation with more readable names, and EXTS
and EXTZ are visually very close to each other with just the S and Z.
They are also following an odd convention where they are ALLCAPS rather
than snake_case like other functions in the spec.
I think this convention comes from early Power specs in Sail, which
influenced Sail MIPS and CHERI-MIPS, but I don't think it's a very
good convention we should be keeping in sail-riscv
Diffstat (limited to 'model/riscv_pmp_regs.sail')
| -rw-r--r-- | model/riscv_pmp_regs.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/model/riscv_pmp_regs.sail b/model/riscv_pmp_regs.sail index 9b76c2d..d022006 100644 --- a/model/riscv_pmp_regs.sail +++ b/model/riscv_pmp_regs.sail @@ -221,4 +221,4 @@ function pmpWriteCfgReg(n, v) = { function pmpWriteAddr(locked: bool, tor_locked: bool, reg: xlenbits, v: xlenbits) -> xlenbits = if sizeof(xlen) == 32 then { if (locked | tor_locked) then reg else v } - else { if (locked | tor_locked) then reg else EXTZ(v[53..0]) } + else { if (locked | tor_locked) then reg else zero_extend(v[53..0]) } |