diff options
| author | Alasdair <alasdair.armstrong@cl.cam.ac.uk> | 2023-12-12 14:55:37 +0000 |
|---|---|---|
| committer | Bill McSpadden <bill@riscv.org> | 2024-01-31 12:38:33 -0600 |
| commit | 563446c477f5e905df905e0d30371a2c4d51d7a5 (patch) | |
| tree | d0f503b96366666ad97eea2a4ba4cbe748e82326 /model/riscv_pmp_regs.sail | |
| parent | d7a3d8012fd579f40e53a29569141d72dd5e0c32 (diff) | |
| download | sail-riscv-563446c477f5e905df905e0d30371a2c4d51d7a5.zip sail-riscv-563446c477f5e905df905e0d30371a2c4d51d7a5.tar.gz sail-riscv-563446c477f5e905df905e0d30371a2c4d51d7a5.tar.bz2 | |
Update bitfield syntax
Use newer bitfield syntax, which has been part of Sail for
a while now. Should in theory be more efficient as it removes
a level of indirection for bitfield accesses.
It's also much more friendly to `sail -fmt`, which has no idea
how to handle the old bitfield syntax.
Diffstat (limited to 'model/riscv_pmp_regs.sail')
| -rw-r--r-- | model/riscv_pmp_regs.sail | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/model/riscv_pmp_regs.sail b/model/riscv_pmp_regs.sail index 9b6355c..04ab309 100644 --- a/model/riscv_pmp_regs.sail +++ b/model/riscv_pmp_regs.sail @@ -144,25 +144,25 @@ val pmpReadCfgReg : forall 'n, 0 <= 'n < 4 . (atom('n)) -> xlenbits function pmpReadCfgReg(n) = { if sizeof(xlen) == 32 then match n { - 0 => append(pmp3cfg.bits(), append(pmp2cfg.bits(), append(pmp1cfg.bits(), pmp0cfg.bits()))), - 1 => append(pmp7cfg.bits(), append(pmp6cfg.bits(), append(pmp5cfg.bits(), pmp4cfg.bits()))), - 2 => append(pmp11cfg.bits(), append(pmp10cfg.bits(), append(pmp9cfg.bits(), pmp8cfg.bits()))), - 3 => append(pmp15cfg.bits(), append(pmp14cfg.bits(), append(pmp13cfg.bits(), pmp12cfg.bits()))), + 0 => append(pmp3cfg.bits, append(pmp2cfg.bits, append(pmp1cfg.bits, pmp0cfg.bits))), + 1 => append(pmp7cfg.bits, append(pmp6cfg.bits, append(pmp5cfg.bits, pmp4cfg.bits))), + 2 => append(pmp11cfg.bits, append(pmp10cfg.bits, append(pmp9cfg.bits, pmp8cfg.bits))), + 3 => append(pmp15cfg.bits, append(pmp14cfg.bits, append(pmp13cfg.bits, pmp12cfg.bits))), _ => internal_error(__FILE__, __LINE__, "Unexpected pmp config reg read") } else match n { // sizeof(xlen) >= 64 - 0 => append(pmp7cfg.bits(), append(pmp6cfg.bits(), append(pmp5cfg.bits(), append(pmp4cfg.bits(), append(pmp3cfg.bits(), append(pmp2cfg.bits(), append(pmp1cfg.bits(), pmp0cfg.bits()))))))), - 2 => append(pmp15cfg.bits(), append(pmp14cfg.bits(), append(pmp13cfg.bits(), append(pmp12cfg.bits(), append(pmp11cfg.bits(), append(pmp10cfg.bits(), append(pmp9cfg.bits(), pmp8cfg.bits()))))))), + 0 => append(pmp7cfg.bits, append(pmp6cfg.bits, append(pmp5cfg.bits, append(pmp4cfg.bits, append(pmp3cfg.bits, append(pmp2cfg.bits, append(pmp1cfg.bits, pmp0cfg.bits))))))), + 2 => append(pmp15cfg.bits, append(pmp14cfg.bits, append(pmp13cfg.bits, append(pmp12cfg.bits, append(pmp11cfg.bits, append(pmp10cfg.bits, append(pmp9cfg.bits, pmp8cfg.bits))))))), _ => internal_error(__FILE__, __LINE__, "Unexpected pmp config reg read") } } /* Helpers to handle locked entries */ function pmpLocked(cfg: Pmpcfg_ent) -> bool = - cfg.L() == 0b1 + cfg[L] == 0b1 function pmpTORLocked(cfg: Pmpcfg_ent) -> bool = - (cfg.L() == 0b1) & (pmpAddrMatchType_of_bits(cfg.A()) == TOR) + (cfg[L] == 0b1) & (pmpAddrMatchType_of_bits(cfg[A]) == TOR) function pmpWriteCfg(cfg: Pmpcfg_ent, v: bits(8)) -> Pmpcfg_ent = if pmpLocked(cfg) then cfg |