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author | Robert Norton <rmn30@cam.ac.uk> | 2019-07-01 12:09:02 +0100 |
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committer | Robert Norton <rmn30@cam.ac.uk> | 2019-07-01 12:09:02 +0100 |
commit | b3a9c7972d7c75b0e133f11def12c3c9f1a090f9 (patch) | |
tree | a6fe631a62c8cb19b364fd8779c8ff6154e280c1 /model/riscv_mem.sail | |
parent | efdbcdb53c9f11cf259443c5768fff168cfe50a0 (diff) | |
parent | 0fbfc08351dfdc2f57c57f78632ce9bef64d109a (diff) | |
download | sail-riscv-b3a9c7972d7c75b0e133f11def12c3c9f1a090f9.zip sail-riscv-b3a9c7972d7c75b0e133f11def12c3c9f1a090f9.tar.gz sail-riscv-b3a9c7972d7c75b0e133f11def12c3c9f1a090f9.tar.bz2 |
Merge remote-tracking branch 'origin/master' into master-cleanup
Diffstat (limited to 'model/riscv_mem.sail')
-rw-r--r-- | model/riscv_mem.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/model/riscv_mem.sail b/model/riscv_mem.sail index c44be53..364c4d6 100644 --- a/model/riscv_mem.sail +++ b/model/riscv_mem.sail @@ -36,7 +36,7 @@ function phys_mem_read forall 'n, 'n > 0. (t : AccessType, addr : xlenbits, widt (Read, None()) => MemException(E_Load_Access_Fault), (_, None()) => MemException(E_SAMO_Access_Fault), (_, Some(v)) => { if get_config_print_mem() - then print_mem("mem[" ^ t ^ "," ^ BitStr(addr) ^ "] -> " ^ BitStr(v)); + then print_mem("mem[" ^ to_str(t) ^ "," ^ BitStr(addr) ^ "] -> " ^ BitStr(v)); MemValue(v) } } } |