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| author | Alasdair <alasdair.armstrong@cl.cam.ac.uk> | 2023-06-29 13:30:11 +0100 |
|---|---|---|
| committer | Bill McSpadden <bill@riscv.org> | 2023-08-01 08:54:15 -0500 |
| commit | 58cac61d9ddde591902c933a9dfa5d8ba3fca6da (patch) | |
| tree | 68b5d44c3008a16af32be9c0e099d8ef1fa39ad5 /model/riscv_mem.sail | |
| parent | ae905fb888cbb21c782bacf86be182d9e20b8895 (diff) | |
| download | sail-riscv-58cac61d9ddde591902c933a9dfa5d8ba3fca6da.zip sail-riscv-58cac61d9ddde591902c933a9dfa5d8ba3fca6da.tar.gz sail-riscv-58cac61d9ddde591902c933a9dfa5d8ba3fca6da.tar.bz2 | |
Rename EXTZ and EXTS
Rename EXTZ to zero_extend and EXTS to sign_extend. Two main reasons
for doing this - it means that the source more closely follows the
descriptions in the documentation with more readable names, and EXTS
and EXTZ are visually very close to each other with just the S and Z.
They are also following an odd convention where they are ALLCAPS rather
than snake_case like other functions in the spec.
I think this convention comes from early Power specs in Sail, which
influenced Sail MIPS and CHERI-MIPS, but I don't think it's a very
good convention we should be keeping in sail-riscv
Diffstat (limited to 'model/riscv_mem.sail')
| -rw-r--r-- | model/riscv_mem.sail | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/model/riscv_mem.sail b/model/riscv_mem.sail index fb3df02..1472589 100644 --- a/model/riscv_mem.sail +++ b/model/riscv_mem.sail @@ -158,7 +158,7 @@ function pmp_mem_read forall 'n, 0 < 'n <= max_mem_access . (t : AccessType(ext_ $ifdef RVFI_DII val rvfi_read : forall 'n, 'n > 0. (xlenbits, atom('n), MemoryOpResult((bits(8 * 'n), mem_meta))) -> unit effect {wreg} function rvfi_read (addr, width, result) = { - rvfi_mem_data->rvfi_mem_addr() = EXTZ(addr); + rvfi_mem_data->rvfi_mem_addr() = zero_extend(addr); rvfi_mem_data_present = true; match result { /* TODO: report tag bit for capability writes and extend mask by one bit. */ @@ -232,7 +232,7 @@ function mem_write_ea (addr, width, aq, rl, con) = { $ifdef RVFI_DII val rvfi_write : forall 'n, 0 < 'n <= max_mem_access . (xlenbits, atom('n), bits(8 * 'n), mem_meta, MemoryOpResult(bool)) -> unit effect {wreg} function rvfi_write (addr, width, value, meta, result) = { - rvfi_mem_data->rvfi_mem_addr() = EXTZ(addr); + rvfi_mem_data->rvfi_mem_addr() = zero_extend(addr); rvfi_mem_data_present = true; match result { /* Log only the memory address (without the value) if the write fails. */ |