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| author | Alasdair Armstrong <alasdair.armstrong@cl.cam.ac.uk> | 2019-08-19 18:49:23 +0100 |
|---|---|---|
| committer | Alasdair Armstrong <alasdair.armstrong@cl.cam.ac.uk> | 2019-08-19 18:53:00 +0100 |
| commit | a381a832bb39bb7571725f75c27dc257762cd693 (patch) | |
| tree | 29c1d4210ffa91e372f94f2567e3f3275b466b4e /model/riscv_jalr_seq.sail | |
| parent | c0c70effa02100c16870251b2a27b79a1cab7331 (diff) | |
| download | sail-riscv-a381a832bb39bb7571725f75c27dc257762cd693.zip sail-riscv-a381a832bb39bb7571725f75c27dc257762cd693.tar.gz sail-riscv-a381a832bb39bb7571725f75c27dc257762cd693.tar.bz2 | |
RISC-V spec, without implicit casts
Diffstat (limited to 'model/riscv_jalr_seq.sail')
| -rw-r--r-- | model/riscv_jalr_seq.sail | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/model/riscv_jalr_seq.sail b/model/riscv_jalr_seq.sail index 5b37c78..884820f 100644 --- a/model/riscv_jalr_seq.sail +++ b/model/riscv_jalr_seq.sail @@ -15,9 +15,8 @@ function clause execute (RISCV_JALR(imm, rs1, rd)) = { RETIRE_FAIL }, Ext_ControlAddr_OK(addr) => { - let target = [addr with 0 = bitzero]; /* clear addr[0] */ - if target[1] & (~ (haveRVC())) - then { + let target = [addr with 0 = bitzero]; /* clear addr[0] */ + if bit_to_bool(target[1]) & ~(haveRVC()) then { handle_mem_exception(target, E_Fetch_Addr_Align); RETIRE_FAIL } else { |