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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-08 15:20:37 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-08 17:14:33 -0800 |
| commit | 5fe7d887ccb0594debbc87078af116eb41e29e36 (patch) | |
| tree | 3dab797ec31ff93ae751e4f19fe55257e5a6e06a /model/riscv_jalr_seq.sail | |
| parent | 8da8797a8fc33e59b73df09b729a97c28dad26c3 (diff) | |
| download | sail-riscv-5fe7d887ccb0594debbc87078af116eb41e29e36.zip sail-riscv-5fe7d887ccb0594debbc87078af116eb41e29e36.tar.gz sail-riscv-5fe7d887ccb0594debbc87078af116eb41e29e36.tar.bz2 | |
Start parameterizing definitions by xlen, which is currently still 64.
Diffstat (limited to 'model/riscv_jalr_seq.sail')
| -rw-r--r-- | model/riscv_jalr_seq.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/model/riscv_jalr_seq.sail b/model/riscv_jalr_seq.sail index fcf9526..d4982c6 100644 --- a/model/riscv_jalr_seq.sail +++ b/model/riscv_jalr_seq.sail @@ -7,7 +7,7 @@ function clause execute (RISCV_JALR(imm, rs1, rd)) = { some manner, but for now, we just keep a reordered definition to improve simulator performance. */ - let newPC : xlenbits = (X(rs1) + EXTS(imm))[63..1] @ 0b0; + let newPC : xlenbits = (X(rs1) + EXTS(imm))[(xlen_val) - 1 .. 1] @ 0b0; if newPC[1] & (~ (haveRVC())) then { handle_mem_exception(newPC, E_Fetch_Addr_Align); false; |