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author | Tim Hutt <timothy.hutt@codasip.com> | 2023-09-16 13:47:00 +0100 |
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committer | Bill McSpadden <bill@riscv.org> | 2023-10-25 09:02:23 -0500 |
commit | 208d441d4e53e0c62d73fac85e7ac9aaf68fac1e (patch) | |
tree | 8cbc73913d9ba74e31f1e11d9b835b01d7db1649 /model/riscv_insts_zfa.sail | |
parent | c90cf2e6eff5fa4ef7b93cc2020166dea7453fc6 (diff) | |
download | sail-riscv-208d441d4e53e0c62d73fac85e7ac9aaf68fac1e.zip sail-riscv-208d441d4e53e0c62d73fac85e7ac9aaf68fac1e.tar.gz sail-riscv-208d441d4e53e0c62d73fac85e7ac9aaf68fac1e.tar.bz2 |
Simplify softfloat interface by removing write_fflags
Instead of keeping a mirror register in sync with fflags, just return the new flags.
Diffstat (limited to 'model/riscv_insts_zfa.sail')
-rw-r--r-- | model/riscv_insts_zfa.sail | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/model/riscv_insts_zfa.sail b/model/riscv_insts_zfa.sail index 3cbee5e..ad8a6b4 100644 --- a/model/riscv_insts_zfa.sail +++ b/model/riscv_insts_zfa.sail @@ -416,7 +416,7 @@ function clause execute (RISCV_FROUND_H(rs1, rm, rd)) = { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_H) = riscv_f16roundToInt(rm_3b, rs1_val_H, false); - write_fflags(fflags); + accrue_fflags(fflags); F_H(rd) = rd_val_H; RETIRE_SUCCESS } @@ -444,7 +444,7 @@ function clause execute (RISCV_FROUNDNX_H(rs1, rm, rd)) = { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_H) = riscv_f16roundToInt(rm_3b, rs1_val_H, true); - write_fflags(fflags); + accrue_fflags(fflags); F_H(rd) = rd_val_H; RETIRE_SUCCESS } @@ -472,7 +472,7 @@ function clause execute (RISCV_FROUND_S(rs1, rm, rd)) = { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_S) = riscv_f32roundToInt(rm_3b, rs1_val_S, false); - write_fflags(fflags); + accrue_fflags(fflags); F_S(rd) = rd_val_S; RETIRE_SUCCESS } @@ -500,7 +500,7 @@ function clause execute (RISCV_FROUNDNX_S(rs1, rm, rd)) = { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_S) = riscv_f32roundToInt(rm_3b, rs1_val_S, true); - write_fflags(fflags); + accrue_fflags(fflags); F_S(rd) = rd_val_S; RETIRE_SUCCESS } @@ -528,7 +528,7 @@ function clause execute (RISCV_FROUND_D(rs1, rm, rd)) = { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_D) = riscv_f64roundToInt(rm_3b, rs1_val_D, false); - write_fflags(fflags); + accrue_fflags(fflags); F(rd) = rd_val_D; RETIRE_SUCCESS } @@ -556,7 +556,7 @@ function clause execute (RISCV_FROUNDNX_D(rs1, rm, rd)) = { let rm_3b = encdec_rounding_mode(rm'); let (fflags, rd_val_D) = riscv_f64roundToInt(rm_3b, rs1_val_D, true); - write_fflags(fflags); + accrue_fflags(fflags); F_D(rd) = rd_val_D; RETIRE_SUCCESS } @@ -627,7 +627,7 @@ function clause execute(RISCV_FLEQ_H(rs2, rs1, rd)) = { let (fflags, rd_val) : (bits_fflags, bool) = riscv_f16Le_quiet (rs1_val_H, rs2_val_H); - write_fflags(fflags); + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } @@ -651,7 +651,7 @@ function clause execute(RISCV_FLTQ_H(rs2, rs1, rd)) = { let (fflags, rd_val) : (bits_fflags, bool) = riscv_f16Lt_quiet (rs1_val_H, rs2_val_H); - write_fflags(fflags); + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } @@ -675,7 +675,7 @@ function clause execute(RISCV_FLEQ_S(rs2, rs1, rd)) = { let (fflags, rd_val) : (bits_fflags, bool) = riscv_f32Le_quiet (rs1_val_S, rs2_val_S); - write_fflags(fflags); + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } @@ -699,7 +699,7 @@ function clause execute(RISCV_FLTQ_S(rs2, rs1, rd)) = { let (fflags, rd_val) : (bits_fflags, bool) = riscv_f32Lt_quiet (rs1_val_S, rs2_val_S); - write_fflags(fflags); + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } @@ -724,7 +724,7 @@ function clause execute(RISCV_FLEQ_D(rs2, rs1, rd)) = { let (fflags, rd_val) : (bits_fflags, bool) = riscv_f64Le_quiet (rs1_val_D, rs2_val_D); - write_fflags(fflags); + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } @@ -748,7 +748,7 @@ function clause execute(RISCV_FLTQ_D(rs2, rs1, rd)) = { let (fflags, rd_val) : (bits_fflags, bool) = riscv_f64Lt_quiet (rs1_val_D, rs2_val_D); - write_fflags(fflags); + accrue_fflags(fflags); X(rd) = zero_extend(bool_to_bits(rd_val)); RETIRE_SUCCESS } @@ -828,7 +828,7 @@ mapping clause assembly = RISCV_FCVTMOD_W_D(rs1, rd) function clause execute(RISCV_FCVTMOD_W_D(rs1, rd)) = { let rs1_val_D = F_D(rs1); let (fflags, rd_val) = fcvtmod_helper(rs1_val_D); - write_fflags(fflags); + accrue_fflags(fflags); X(rd) = sign_extend(rd_val); RETIRE_SUCCESS } |