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| author | Tim Hutt <timothy.hutt@codasip.com> | 2024-05-14 16:14:14 +0100 |
|---|---|---|
| committer | Alasdair Armstrong <alasdair.armstrong@googlemail.com> | 2024-05-15 17:31:25 +0100 |
| commit | a71fee30035e6d504b156cda0802902345766e70 (patch) | |
| tree | c22a0d6a5004a90ac756a87de2899cb06848ba2f /model/riscv_insts_vext_vm.sail | |
| parent | e1242d851d6b27b357bfb31d46c8f08e18fb768b (diff) | |
| download | sail-riscv-a71fee30035e6d504b156cda0802902345766e70.zip sail-riscv-a71fee30035e6d504b156cda0802902345766e70.tar.gz sail-riscv-a71fee30035e6d504b156cda0802902345766e70.tar.bz2 | |
Handle 34-bit PMP address overflow
The existing PMP code could not handle physical addresses above 32 bits on RV32, which are possible since Sv32 has 34-bit physical addresses, and the PMP registers are in units of 4 bytes, so they can encode 34-bit addresses.
This fixes that by delaying the *4 until the comparison where it can be done using `nat` instead of `xlenbits` which it would overflow.
Diffstat (limited to 'model/riscv_insts_vext_vm.sail')
0 files changed, 0 insertions, 0 deletions