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| author | Alasdair <alasdair.armstrong@cl.cam.ac.uk> | 2023-12-12 14:55:37 +0000 |
|---|---|---|
| committer | Bill McSpadden <bill@riscv.org> | 2024-01-31 12:38:33 -0600 |
| commit | 563446c477f5e905df905e0d30371a2c4d51d7a5 (patch) | |
| tree | d0f503b96366666ad97eea2a4ba4cbe748e82326 /model/riscv_insts_vext_red.sail | |
| parent | d7a3d8012fd579f40e53a29569141d72dd5e0c32 (diff) | |
| download | sail-riscv-563446c477f5e905df905e0d30371a2c4d51d7a5.zip sail-riscv-563446c477f5e905df905e0d30371a2c4d51d7a5.tar.gz sail-riscv-563446c477f5e905df905e0d30371a2c4d51d7a5.tar.bz2 | |
Update bitfield syntax
Use newer bitfield syntax, which has been part of Sail for
a while now. Should in theory be more efficient as it removes
a level of indirection for bitfield accesses.
It's also much more friendly to `sail -fmt`, which has no idea
how to handle the old bitfield syntax.
Diffstat (limited to 'model/riscv_insts_vext_red.sail')
| -rwxr-xr-x | model/riscv_insts_vext_red.sail | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/model/riscv_insts_vext_red.sail b/model/riscv_insts_vext_red.sail index be6afc3..80ee8f2 100755 --- a/model/riscv_insts_vext_red.sail +++ b/model/riscv_insts_vext_red.sail @@ -190,7 +190,7 @@ mapping clause encdec = RFVVTYPE(funct6, vm, vs2, vs1, vd) if haveVExt() val process_rfvv_single: forall 'n 'm 'p, 'n >= 0 & 'm in {8, 16, 32, 64}. (rfvvfunct6, bits(1), regidx, regidx, regidx, int('n), int('m), int('p)) -> Retired function process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) = { - let rm_3b = fcsr.FRM(); + let rm_3b = fcsr[FRM]; let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ if illegal_fp_reduction(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; @@ -229,7 +229,7 @@ function process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_po val process_rfvv_widen: forall 'n 'm 'p, 'n >= 0 & 'm in {8, 16, 32, 64}. (rfvvfunct6, bits(1), regidx, regidx, regidx, int('n), int('m), int('p)) -> Retired function process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) = { - let rm_3b = fcsr.FRM(); + let rm_3b = fcsr[FRM]; let SEW_widen = SEW * 2; let LMUL_pow_widen = LMUL_pow + 1; let num_elem_vd = get_num_elem(0, SEW_widen); /* vd regardless of LMUL setting */ |