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authorPrashanth Mundkur <prashanth.mundkur@gmail.com>2019-05-03 13:35:22 -0700
committerPrashanth Mundkur <prashanth.mundkur@gmail.com>2019-05-03 13:36:02 -0700
commit860b8675bed29617bae45cdd37026feaea7c84b2 (patch)
treee9b890ec35fb5ed3357c874bbf255c57c820b1a5 /model/riscv_insts_mext.sail
parenta0818796b4ad4340812805bdc9d4281786ab9cf4 (diff)
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Minor formatting cleanup and remove obsolete comments.
Diffstat (limited to 'model/riscv_insts_mext.sail')
-rw-r--r--model/riscv_insts_mext.sail2
1 files changed, 1 insertions, 1 deletions
diff --git a/model/riscv_insts_mext.sail b/model/riscv_insts_mext.sail
index cab8d9c..b133ac2 100644
--- a/model/riscv_insts_mext.sail
+++ b/model/riscv_insts_mext.sail
@@ -2,7 +2,7 @@
/* This file specifies the instructions in the 'M' extension. */
/* ****************************************************************** */
-/* FIXME: separate these out into separate ast variants */
+
union clause ast = MUL : (regbits, regbits, regbits, bool, bool, bool)
mapping encdec_mul_op : (bool, bool, bool) <-> bits(3) = {