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author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-19 15:49:56 -0800 |
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committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-19 15:49:56 -0800 |
commit | 6a4eb9211bab5070dc55cea9046e1ffc4e20eafc (patch) | |
tree | 2c9f667f8852a89f66896bbb62b4c09deceea034 /model/riscv_insts_mext.sail | |
parent | a238acdcd83f2db3c6d549775f16ac8b4ad2291e (diff) | |
download | sail-riscv-6a4eb9211bab5070dc55cea9046e1ffc4e20eafc.zip sail-riscv-6a4eb9211bab5070dc55cea9046e1ffc4e20eafc.tar.gz sail-riscv-6a4eb9211bab5070dc55cea9046e1ffc4e20eafc.tar.bz2 |
Use sizeof xlen instead of the value definitions of xlen.
Diffstat (limited to 'model/riscv_insts_mext.sail')
-rw-r--r-- | model/riscv_insts_mext.sail | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/model/riscv_insts_mext.sail b/model/riscv_insts_mext.sail index 371966f..cab8d9c 100644 --- a/model/riscv_insts_mext.sail +++ b/model/riscv_insts_mext.sail @@ -22,10 +22,10 @@ function clause execute (MUL(rs2, rs1, rd, high, signed1, signed2)) = { let rs2_val = X(rs2); let rs1_int : int = if signed1 then signed(rs1_val) else unsigned(rs1_val); let rs2_int : int = if signed2 then signed(rs2_val) else unsigned(rs2_val); - let result_wide = to_bits(2 * xlen, rs1_int * rs2_int); + let result_wide = to_bits(2 * sizeof(xlen), rs1_int * rs2_int); let result = if high - then result_wide[(2 * xlen - 1) .. xlen] - else result_wide[(xlen - 1) .. 0]; + then result_wide[(2 * sizeof(xlen) - 1) .. sizeof(xlen)] + else result_wide[(sizeof(xlen) - 1) .. 0]; X(rd) = result; true } else { @@ -59,7 +59,7 @@ function clause execute (DIV(rs2, rs1, rd, s)) = { let q : int = if rs2_int == 0 then -1 else quot_round_zero(rs1_int, rs2_int); /* check for signed overflow */ let q': int = if s & q > xlen_max_signed then xlen_min_signed else q; - X(rd) = to_bits(xlen, q'); + X(rd) = to_bits(sizeof(xlen), q'); true } else { handle_illegal(); @@ -89,7 +89,7 @@ function clause execute (REM(rs2, rs1, rd, s)) = { let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val); let r : int = if rs2_int == 0 then rs1_int else rem_round_zero(rs1_int, rs2_int); /* signed overflow case returns zero naturally as required due to -1 divisor */ - X(rd) = to_bits(xlen, r); + X(rd) = to_bits(sizeof(xlen), r); true } else { handle_illegal(); @@ -104,9 +104,9 @@ mapping clause assembly = REM(rs2, rs1, rd, s) union clause ast = MULW : (regbits, regbits, regbits) mapping clause encdec = MULW(rs2, rs1, rd) - if xlen == 64 + if sizeof(xlen) == 64 <-> 0b0000001 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0111011 - if xlen == 64 + if sizeof(xlen) == 64 function clause execute (MULW(rs2, rs1, rd)) = { if haveMulDiv() then { @@ -126,17 +126,17 @@ function clause execute (MULW(rs2, rs1, rd)) = { } mapping clause assembly = MULW(rs2, rs1, rd) - if xlen == 64 + if sizeof(xlen) == 64 <-> "mulw" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) - if xlen == 64 + if sizeof(xlen) == 64 /* ****************************************************************** */ union clause ast = DIVW : (regbits, regbits, regbits, bool) mapping clause encdec = DIVW(rs2, rs1, rd, s) - if xlen == 64 + if sizeof(xlen) == 64 <-> 0b0000001 @ rs2 @ rs1 @ 0b10 @ bool_not_bits(s) @ rd @ 0b0111011 - if xlen == 64 + if sizeof(xlen) == 64 function clause execute (DIVW(rs2, rs1, rd, s)) = { if haveMulDiv() then { @@ -156,17 +156,17 @@ function clause execute (DIVW(rs2, rs1, rd, s)) = { } mapping clause assembly = DIVW(rs2, rs1, rd, s) - if xlen == 64 + if sizeof(xlen) == 64 <-> "div" ^ maybe_not_u(s) ^ "w" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) - if xlen == 64 + if sizeof(xlen) == 64 /* ****************************************************************** */ union clause ast = REMW : (regbits, regbits, regbits, bool) mapping clause encdec = REMW(rs2, rs1, rd, s) - if xlen == 64 + if sizeof(xlen) == 64 <-> 0b0000001 @ rs2 @ rs1 @ 0b11 @ bool_not_bits(s) @ rd @ 0b0111011 - if xlen == 64 + if sizeof(xlen) == 64 function clause execute (REMW(rs2, rs1, rd, s)) = { if haveMulDiv() then { @@ -185,6 +185,6 @@ function clause execute (REMW(rs2, rs1, rd, s)) = { } mapping clause assembly = REMW(rs2, rs1, rd, s) - if xlen == 64 + if sizeof(xlen) == 64 <-> "rem" ^ maybe_not_u(s) ^ "w" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) - if xlen == 64 + if sizeof(xlen) == 64 |