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author | Alasdair <alasdair.armstrong@cl.cam.ac.uk> | 2023-06-29 13:30:11 +0100 |
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committer | Bill McSpadden <bill@riscv.org> | 2023-08-01 08:54:15 -0500 |
commit | 58cac61d9ddde591902c933a9dfa5d8ba3fca6da (patch) | |
tree | 68b5d44c3008a16af32be9c0e099d8ef1fa39ad5 /model/riscv_insts_mext.sail | |
parent | ae905fb888cbb21c782bacf86be182d9e20b8895 (diff) | |
download | sail-riscv-58cac61d9ddde591902c933a9dfa5d8ba3fca6da.zip sail-riscv-58cac61d9ddde591902c933a9dfa5d8ba3fca6da.tar.gz sail-riscv-58cac61d9ddde591902c933a9dfa5d8ba3fca6da.tar.bz2 |
Rename EXTZ and EXTS
Rename EXTZ to zero_extend and EXTS to sign_extend. Two main reasons
for doing this - it means that the source more closely follows the
descriptions in the documentation with more readable names, and EXTS
and EXTZ are visually very close to each other with just the S and Z.
They are also following an odd convention where they are ALLCAPS rather
than snake_case like other functions in the spec.
I think this convention comes from early Power specs in Sail, which
influenced Sail MIPS and CHERI-MIPS, but I don't think it's a very
good convention we should be keeping in sail-riscv
Diffstat (limited to 'model/riscv_insts_mext.sail')
-rw-r--r-- | model/riscv_insts_mext.sail | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/model/riscv_insts_mext.sail b/model/riscv_insts_mext.sail index de0e093..7cee337 100644 --- a/model/riscv_insts_mext.sail +++ b/model/riscv_insts_mext.sail @@ -186,7 +186,7 @@ function clause execute (MULW(rs2, rs1, rd)) = { let rs2_int : int = signed(rs2_val); /* to_bits requires expansion to 64 bits followed by truncation */ let result32 = to_bits(64, rs1_int * rs2_int)[31..0]; - let result : xlenbits = EXTS(result32); + let result : xlenbits = sign_extend(result32); X(rd) = result; RETIRE_SUCCESS } else { @@ -217,7 +217,7 @@ function clause execute (DIVW(rs2, rs1, rd, s)) = { let q : int = if rs2_int == 0 then -1 else quot_round_zero(rs1_int, rs2_int); /* check for signed overflow */ let q': int = if s & q > (2 ^ 31 - 1) then (0 - 2^31) else q; - X(rd) = EXTS(to_bits(32, q')); + X(rd) = sign_extend(to_bits(32, q')); RETIRE_SUCCESS } else { handle_illegal(); @@ -246,7 +246,7 @@ function clause execute (REMW(rs2, rs1, rd, s)) = { let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val); let r : int = if rs2_int == 0 then rs1_int else rem_round_zero(rs1_int, rs2_int); /* signed overflow case returns zero naturally as required due to -1 divisor */ - X(rd) = EXTS(to_bits(32, r)); + X(rd) = sign_extend(to_bits(32, r)); RETIRE_SUCCESS } else { handle_illegal(); |