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| author | Tim Hutt <timothy.hutt@codasip.com> | 2023-09-23 19:57:38 +0100 |
|---|---|---|
| committer | Bill McSpadden <bill@riscv.org> | 2023-10-11 20:50:13 -0500 |
| commit | 51a6c967fb320c2d47a3630b1f392e54eb69c3d7 (patch) | |
| tree | cd864017e11911f4e86c32e7a437993a9ce05a58 /model/riscv_insts_mext.sail | |
| parent | 532714a6c71b47a91176eb90fef3b3b049c52fce (diff) | |
| download | sail-riscv-51a6c967fb320c2d47a3630b1f392e54eb69c3d7.zip sail-riscv-51a6c967fb320c2d47a3630b1f392e54eb69c3d7.tar.gz sail-riscv-51a6c967fb320c2d47a3630b1f392e54eb69c3d7.tar.bz2 | |
Implement menvcfg
This implements the m/senvcfg(h) CSRs. This CSR is used to enable/disable extensions and behaviours for lower privilege modes. Currently the only implemented bit is FIOM which affects how fences work.
It also affects how atomic memory accesses work in non-cacheable regions, but the model does not currently support PMAs so that can't easily be implemented.
Diffstat (limited to 'model/riscv_insts_mext.sail')
0 files changed, 0 insertions, 0 deletions