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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-05-10 11:04:48 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-05-10 11:04:48 -0700 |
| commit | 374a1e221c32a2856e31dfcd44abf539cc07a425 (patch) | |
| tree | 83dcb91722eac7080b46ade680ada2592b91efd7 /model/riscv_insts_mext.sail | |
| parent | c3bcac091312173ff87beccb7709b5ab0eeccfaa (diff) | |
| download | sail-riscv-374a1e221c32a2856e31dfcd44abf539cc07a425.zip sail-riscv-374a1e221c32a2856e31dfcd44abf539cc07a425.tar.gz sail-riscv-374a1e221c32a2856e31dfcd44abf539cc07a425.tar.bz2 | |
Rename regbits to regidx, to clarify the type is an index and not the contents of a register.
Diffstat (limited to 'model/riscv_insts_mext.sail')
| -rw-r--r-- | model/riscv_insts_mext.sail | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/model/riscv_insts_mext.sail b/model/riscv_insts_mext.sail index 509a7d7..4830f93 100644 --- a/model/riscv_insts_mext.sail +++ b/model/riscv_insts_mext.sail @@ -3,7 +3,7 @@ /* ****************************************************************** */ -union clause ast = MUL : (regbits, regbits, regbits, bool, bool, bool) +union clause ast = MUL : (regidx, regidx, regidx, bool, bool, bool) mapping encdec_mul_op : (bool, bool, bool) <-> bits(3) = { (false, true, true) <-> 0b000, @@ -45,7 +45,7 @@ mapping clause assembly = MUL(rs2, rs1, rd, high, signed1, signed2) <-> mul_mnemonic(high, signed1, signed2) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) /* ****************************************************************** */ -union clause ast = DIV : (regbits, regbits, regbits, bool) +union clause ast = DIV : (regidx, regidx, regidx, bool) mapping clause encdec = DIV(rs2, rs1, rd, s) <-> 0b0000001 @ rs2 @ rs1 @ 0b10 @ bool_not_bits(s) @ rd @ 0b0110011 @@ -76,7 +76,7 @@ mapping clause assembly = DIV(rs2, rs1, rd, s) <-> "div" ^ maybe_not_u(s) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) /* ****************************************************************** */ -union clause ast = REM : (regbits, regbits, regbits, bool) +union clause ast = REM : (regidx, regidx, regidx, bool) mapping clause encdec = REM(rs2, rs1, rd, s) <-> 0b0000001 @ rs2 @ rs1 @ 0b11 @ bool_not_bits(s) @ rd @ 0b0110011 @@ -101,7 +101,7 @@ mapping clause assembly = REM(rs2, rs1, rd, s) <-> "rem" ^ maybe_not_u(s) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) /* ****************************************************************** */ -union clause ast = MULW : (regbits, regbits, regbits) +union clause ast = MULW : (regidx, regidx, regidx) mapping clause encdec = MULW(rs2, rs1, rd) if sizeof(xlen) == 64 @@ -131,7 +131,7 @@ mapping clause assembly = MULW(rs2, rs1, rd) if sizeof(xlen) == 64 /* ****************************************************************** */ -union clause ast = DIVW : (regbits, regbits, regbits, bool) +union clause ast = DIVW : (regidx, regidx, regidx, bool) mapping clause encdec = DIVW(rs2, rs1, rd, s) if sizeof(xlen) == 64 @@ -161,7 +161,7 @@ mapping clause assembly = DIVW(rs2, rs1, rd, s) if sizeof(xlen) == 64 /* ****************************************************************** */ -union clause ast = REMW : (regbits, regbits, regbits, bool) +union clause ast = REMW : (regidx, regidx, regidx, bool) mapping clause encdec = REMW(rs2, rs1, rd, s) if sizeof(xlen) == 64 |