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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-08-09 18:01:03 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-08-09 18:01:03 -0700 |
| commit | 50033a227e89d679cd42b070e7e096586275357c (patch) | |
| tree | 732b4476719afdb21b21b5430566ea4833d5dade /model/riscv_insts_base.sail | |
| parent | d3b0d1fd89e5ba2807a87f72e77510c719e60281 (diff) | |
| download | sail-riscv-50033a227e89d679cd42b070e7e096586275357c.zip sail-riscv-50033a227e89d679cd42b070e7e096586275357c.tar.gz sail-riscv-50033a227e89d679cd42b070e7e096586275357c.tar.bz2 | |
Allow accumulation of information during page-table-walk for extensions.
Diffstat (limited to 'model/riscv_insts_base.sail')
| -rw-r--r-- | model/riscv_insts_base.sail | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/model/riscv_insts_base.sail b/model/riscv_insts_base.sail index bdd60ce..d0346b5 100644 --- a/model/riscv_insts_base.sail +++ b/model/riscv_insts_base.sail @@ -324,8 +324,8 @@ function clause execute(LOAD(imm, rs1, rd, is_unsigned, width, aq, rl)) = { if check_misaligned(vaddr, width) then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } else match translateAddr(vaddr, Read(Data)) { - TR_Failure(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr) => + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => match (width, sizeof(xlen)) { (BYTE, _) => process_load(rd, vaddr, mem_read(Read(Data), addr, 1, aq, rl, false), is_unsigned), @@ -379,8 +379,8 @@ function clause execute (STORE(imm, rs2, rs1, width, aq, rl)) = { if check_misaligned(vaddr, width) then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL } else match translateAddr(vaddr, Write(Data)) { - TR_Failure(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, - TR_Address(addr) => { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { let eares : MemoryOpResult(unit) = match width { BYTE => mem_write_ea(addr, 1, aq, rl, false), HALF => mem_write_ea(addr, 2, aq, rl, false), |