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author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-08-20 09:55:29 -0700 |
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committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-08-20 09:55:29 -0700 |
commit | 3d75de27c854072b82493a73e01c69d27624bf94 (patch) | |
tree | 1264477fa4424b4b0a9aba7ca2adcb1f4c5b25a3 /model/riscv_insts_base.sail | |
parent | a381a832bb39bb7571725f75c27dc257762cd693 (diff) | |
download | sail-riscv-3d75de27c854072b82493a73e01c69d27624bf94.zip sail-riscv-3d75de27c854072b82493a73e01c69d27624bf94.tar.gz sail-riscv-3d75de27c854072b82493a73e01c69d27624bf94.tar.bz2 |
Whitespace fixes to nuke tabs.no_casts
Diffstat (limited to 'model/riscv_insts_base.sail')
-rw-r--r-- | model/riscv_insts_base.sail | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/model/riscv_insts_base.sail b/model/riscv_insts_base.sail index a0858bf..e138e72 100644 --- a/model/riscv_insts_base.sail +++ b/model/riscv_insts_base.sail @@ -123,7 +123,7 @@ function clause execute (BTYPE(imm, rs2, rs1, op)) = { RETIRE_FAIL }, Ext_ControlAddr_OK(target) => { - if bit_to_bool(target[1]) & (~ (haveRVC())) then { + if bit_to_bool(target[1]) & (~ (haveRVC())) then { handle_mem_exception(target, E_Fetch_Addr_Align); RETIRE_FAIL; } else { @@ -309,9 +309,9 @@ function check_misaligned(vaddr : xlenbits, width : word_width) -> bool = if plat_enable_misaligned_access() then false else match width { BYTE => false, - HALF => vaddr[0] == bitone, - WORD => vaddr[0] == bitone | vaddr[1] == bitone, - DOUBLE => vaddr[0] == bitone | vaddr[1] == bitone | vaddr[2] == bitone + HALF => vaddr[0] == bitone, + WORD => vaddr[0] == bitone | vaddr[1] == bitone, + DOUBLE => vaddr[0] == bitone | vaddr[1] == bitone | vaddr[2] == bitone } function clause execute(LOAD(imm, rs1, rd, is_unsigned, width, aq, rl)) = { @@ -785,8 +785,8 @@ function clause execute SFENCE_VMA(rs1, rs2) = { match cur_privilege { User => { handle_illegal(); RETIRE_FAIL }, Supervisor => match (architecture(get_mstatus_SXL(mstatus)), mstatus.TVM()) { - (Some(_), 0b1) => { handle_illegal(); RETIRE_FAIL }, - (Some(_), 0b0) => { flush_TLB(asid, addr); RETIRE_SUCCESS }, + (Some(_), 0b1) => { handle_illegal(); RETIRE_FAIL }, + (Some(_), 0b0) => { flush_TLB(asid, addr); RETIRE_SUCCESS }, (_, _) => internal_error("unimplemented sfence architecture") }, Machine => { flush_TLB(asid, addr); RETIRE_SUCCESS } |