First commit with code for F and D extensions (detail follows)

>----------------
Modified existing file:  riscv_sys_regs.sail

Added predicates 'haveFExt()' and 'haveDExt()'
Similar to existing 'haveNExt()', 'haveAtomics()', etc.

>----------------
New files:  riscv_flen_F.sail and riscv_flen_D.sail

These are analogous to existing: riscv_xlen32.sail and riscv_xlen64.sail

>----------------
New file:  riscv_freg_type.sail

This is analogous to existing: riscv_reg_type.sail

>----------------
New file:  riscv_fdext_regs.sail

This is the definition of the floating-point reg file, analogous to
existing: riscv_regs.sail

>----------------
New file:  riscv_insts_fdext.sail

This is the spec of F and D instructions.

The file has a section separated by /* **** */ lines
for each related group of instructions.
Each section contains:
    union clause ast ...
    mapping clause encdec ...
    function clause execute ...
    mapping clause assembly ...

Finished all the ast, encdec, and assembly sections.

For the execute sections:
- Finished LOAD_FP and STORE_FP
- For FADD_S/FSUB_S/FMUL_S/FDIV_S: done, assuming certain primitives
    for the actual arithmetic, which have to be linked into Berkeley
    softloat.
- Rest of them have placeholders that treat them as illegal instrs.

Todo:
- Finish 'function clause execute' for remaining instructions,
    and collect list of primitives needed (based on softfloat)
- Fix up Makefile to include these new files, make sure everything compiles.
- Connect softfloat, and run ISA tests.

1 files changed, 5 insertions, 0 deletions

diff --git a/model/riscv_flen_D.sail b/model/riscv_flen_D.sail
new file mode 100644
index 0000000..f093c9f
--- /dev/null
+++ b/model/riscv_flen_D.sail
@@ -0,0 +1,5 @@
+/* Define the FLEN value for the 'D' extension. */
+
+type flen       : Int = 64
+type flen_bytes : Int = 8
+type flenbits         = bits(xlen)