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| author | Robert Norton <rmn30@cam.ac.uk> | 2019-07-19 11:21:40 +0100 |
|---|---|---|
| committer | Robert Norton <rmn30@cam.ac.uk> | 2019-07-19 11:38:25 +0100 |
| commit | ad348876ca17529c4d7fe2f3d2ec227f9f3026e1 (patch) | |
| tree | 4359244f3e810470c646e8463dfc2b0b7661f433 /model/riscv_fetch_rvfi.sail | |
| parent | 9735f8824f8a58debf49ac15c6bb1232f3ade499 (diff) | |
| download | sail-riscv-ad348876ca17529c4d7fe2f3d2ec227f9f3026e1.zip sail-riscv-ad348876ca17529c4d7fe2f3d2ec227f9f3026e1.tar.gz sail-riscv-ad348876ca17529c4d7fe2f3d2ec227f9f3026e1.tar.bz2 | |
Add a new pc access function to get the architectural PC: on CHERI this is not what is in the PC register because the architectural PC is the offset of PCC and the PC register stores the absolute PC (at present -- may review this decision in future). This allows fix for AUIPC and RVFI reported PC.master-cleanup
Diffstat (limited to 'model/riscv_fetch_rvfi.sail')
| -rw-r--r-- | model/riscv_fetch_rvfi.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/model/riscv_fetch_rvfi.sail b/model/riscv_fetch_rvfi.sail index 03b6010..c2a5e74 100644 --- a/model/riscv_fetch_rvfi.sail +++ b/model/riscv_fetch_rvfi.sail @@ -5,7 +5,7 @@ function fetch() -> FetchResult = else { let i = rvfi_instruction.rvfi_insn(); rvfi_exec->rvfi_order() = minstret; - rvfi_exec->rvfi_pc_rdata() = EXTZ(PC); + rvfi_exec->rvfi_pc_rdata() = EXTZ(get_arch_pc()); rvfi_exec->rvfi_insn() = EXTZ(i); /* TODO: should we write these even if they're not really registers? */ |