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| author | Alasdair <alasdair.armstrong@cl.cam.ac.uk> | 2023-06-29 13:30:11 +0100 |
|---|---|---|
| committer | Bill McSpadden <bill@riscv.org> | 2023-08-01 08:54:15 -0500 |
| commit | 58cac61d9ddde591902c933a9dfa5d8ba3fca6da (patch) | |
| tree | 68b5d44c3008a16af32be9c0e099d8ef1fa39ad5 /model/riscv_fetch_rvfi.sail | |
| parent | ae905fb888cbb21c782bacf86be182d9e20b8895 (diff) | |
| download | sail-riscv-58cac61d9ddde591902c933a9dfa5d8ba3fca6da.zip sail-riscv-58cac61d9ddde591902c933a9dfa5d8ba3fca6da.tar.gz sail-riscv-58cac61d9ddde591902c933a9dfa5d8ba3fca6da.tar.bz2 | |
Rename EXTZ and EXTS
Rename EXTZ to zero_extend and EXTS to sign_extend. Two main reasons
for doing this - it means that the source more closely follows the
descriptions in the documentation with more readable names, and EXTS
and EXTZ are visually very close to each other with just the S and Z.
They are also following an odd convention where they are ALLCAPS rather
than snake_case like other functions in the spec.
I think this convention comes from early Power specs in Sail, which
influenced Sail MIPS and CHERI-MIPS, but I don't think it's a very
good convention we should be keeping in sail-riscv
Diffstat (limited to 'model/riscv_fetch_rvfi.sail')
| -rw-r--r-- | model/riscv_fetch_rvfi.sail | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/model/riscv_fetch_rvfi.sail b/model/riscv_fetch_rvfi.sail index de17b8f..b036c1b 100644 --- a/model/riscv_fetch_rvfi.sail +++ b/model/riscv_fetch_rvfi.sail @@ -70,9 +70,9 @@ function fetch() -> FetchResult = { rvfi_inst_data->rvfi_order() = minstret; - rvfi_pc_data->rvfi_pc_rdata() = EXTZ(get_arch_pc()); - rvfi_inst_data->rvfi_mode() = EXTZ(privLevel_to_bits(cur_privilege)); - rvfi_inst_data->rvfi_ixl() = EXTZ(misa.MXL()); + rvfi_pc_data->rvfi_pc_rdata() = zero_extend(get_arch_pc()); + rvfi_inst_data->rvfi_mode() = zero_extend(privLevel_to_bits(cur_privilege)); + rvfi_inst_data->rvfi_ixl() = zero_extend(misa.MXL()); /* First allow extensions to check pc */ match ext_fetch_check_pc(PC, PC) { @@ -85,7 +85,7 @@ function fetch() -> FetchResult = { TR_Failure(e, _) => F_Error(e, PC), TR_Address(_, _) => { let i = rvfi_instruction.rvfi_insn(); - rvfi_inst_data->rvfi_insn() = EXTZ(i); + rvfi_inst_data->rvfi_insn() = zero_extend(i); if (i[1 .. 0] != 0b11) then F_RVC(i[15 .. 0]) else { |