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| author | Alasdair <alasdair.armstrong@cl.cam.ac.uk> | 2023-12-12 14:55:37 +0000 |
|---|---|---|
| committer | Bill McSpadden <bill@riscv.org> | 2024-01-31 12:38:33 -0600 |
| commit | 563446c477f5e905df905e0d30371a2c4d51d7a5 (patch) | |
| tree | d0f503b96366666ad97eea2a4ba4cbe748e82326 /model/riscv_fetch_rvfi.sail | |
| parent | d7a3d8012fd579f40e53a29569141d72dd5e0c32 (diff) | |
| download | sail-riscv-563446c477f5e905df905e0d30371a2c4d51d7a5.zip sail-riscv-563446c477f5e905df905e0d30371a2c4d51d7a5.tar.gz sail-riscv-563446c477f5e905df905e0d30371a2c4d51d7a5.tar.bz2 | |
Update bitfield syntax
Use newer bitfield syntax, which has been part of Sail for
a while now. Should in theory be more efficient as it removes
a level of indirection for bitfield accesses.
It's also much more friendly to `sail -fmt`, which has no idea
how to handle the old bitfield syntax.
Diffstat (limited to 'model/riscv_fetch_rvfi.sail')
| -rw-r--r-- | model/riscv_fetch_rvfi.sail | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/model/riscv_fetch_rvfi.sail b/model/riscv_fetch_rvfi.sail index b036c1b..f4567ff 100644 --- a/model/riscv_fetch_rvfi.sail +++ b/model/riscv_fetch_rvfi.sail @@ -69,10 +69,10 @@ /*=======================================================================================*/ function fetch() -> FetchResult = { - rvfi_inst_data->rvfi_order() = minstret; - rvfi_pc_data->rvfi_pc_rdata() = zero_extend(get_arch_pc()); - rvfi_inst_data->rvfi_mode() = zero_extend(privLevel_to_bits(cur_privilege)); - rvfi_inst_data->rvfi_ixl() = zero_extend(misa.MXL()); + rvfi_inst_data[rvfi_order] = minstret; + rvfi_pc_data[rvfi_pc_rdata] = zero_extend(get_arch_pc()); + rvfi_inst_data[rvfi_mode] = zero_extend(privLevel_to_bits(cur_privilege)); + rvfi_inst_data[rvfi_ixl] = zero_extend(misa[MXL]); /* First allow extensions to check pc */ match ext_fetch_check_pc(PC, PC) { @@ -84,7 +84,7 @@ function fetch() -> FetchResult = { else match translateAddr(use_pc, Execute()) { TR_Failure(e, _) => F_Error(e, PC), TR_Address(_, _) => { - let i = rvfi_instruction.rvfi_insn(); + let i = rvfi_instruction[rvfi_insn]; rvfi_inst_data->rvfi_insn() = zero_extend(i); if (i[1 .. 0] != 0b11) then F_RVC(i[15 .. 0]) |