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authorAlexandre Joannou <aj443@cam.ac.uk>2019-06-27 15:57:53 +0100
committerAlexandre Joannou <aj443@cam.ac.uk>2019-06-27 16:15:32 +0100
commit3a57475dfd443d94f631be887cbddae9ed93ede1 (patch)
treefb2967e84c2ae8c1c86df929a79efb3d0109e7f0 /model/riscv_fetch_rvfi.sail
parente09b35a03c64400d050161aa79d1465b1557ea0b (diff)
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Zero extend rather than sign extend rvfi-dii reports (usefull for 32 rvfi-dii comparisons where upper bits are not expected to have information in them)
Diffstat (limited to 'model/riscv_fetch_rvfi.sail')
-rw-r--r--model/riscv_fetch_rvfi.sail8
1 files changed, 4 insertions, 4 deletions
diff --git a/model/riscv_fetch_rvfi.sail b/model/riscv_fetch_rvfi.sail
index 822305a..03b6010 100644
--- a/model/riscv_fetch_rvfi.sail
+++ b/model/riscv_fetch_rvfi.sail
@@ -5,12 +5,12 @@ function fetch() -> FetchResult =
else {
let i = rvfi_instruction.rvfi_insn();
rvfi_exec->rvfi_order() = minstret;
- rvfi_exec->rvfi_pc_rdata() = EXTS(PC);
- rvfi_exec->rvfi_insn() = EXTS(i);
+ rvfi_exec->rvfi_pc_rdata() = EXTZ(PC);
+ rvfi_exec->rvfi_insn() = EXTZ(i);
/* TODO: should we write these even if they're not really registers? */
- rvfi_exec->rvfi_rs1_data() = EXTS(X(i[19 .. 15]));
- rvfi_exec->rvfi_rs2_data() = EXTS(X(i[24 .. 20]));
+ rvfi_exec->rvfi_rs1_data() = EXTZ(X(i[19 .. 15]));
+ rvfi_exec->rvfi_rs2_data() = EXTZ(X(i[24 .. 20]));
rvfi_exec->rvfi_rs1_addr() = sail_zero_extend(i[19 .. 15],8);
rvfi_exec->rvfi_rs2_addr() = sail_zero_extend(i[24 .. 20],8);