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| author | Alasdair Armstrong <alasdair.armstrong@cl.cam.ac.uk> | 2019-08-19 18:49:23 +0100 |
|---|---|---|
| committer | Alasdair Armstrong <alasdair.armstrong@cl.cam.ac.uk> | 2019-08-19 18:53:00 +0100 |
| commit | a381a832bb39bb7571725f75c27dc257762cd693 (patch) | |
| tree | 29c1d4210ffa91e372f94f2567e3f3275b466b4e /model/riscv_fetch.sail | |
| parent | c0c70effa02100c16870251b2a27b79a1cab7331 (diff) | |
| download | sail-riscv-a381a832bb39bb7571725f75c27dc257762cd693.zip sail-riscv-a381a832bb39bb7571725f75c27dc257762cd693.tar.gz sail-riscv-a381a832bb39bb7571725f75c27dc257762cd693.tar.bz2 | |
RISC-V spec, without implicit casts
Diffstat (limited to 'model/riscv_fetch.sail')
| -rw-r--r-- | model/riscv_fetch.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/model/riscv_fetch.sail b/model/riscv_fetch.sail index ae8748c..c52a70d 100644 --- a/model/riscv_fetch.sail +++ b/model/riscv_fetch.sail @@ -12,7 +12,7 @@ function fetch() -> FetchResult = match ext_fetch_check_pc(PC, PC) { Ext_FetchAddr_Error(e) => F_Ext_Error(e), Ext_FetchAddr_OK(use_pc) => { - if (use_pc[0] != 0b0 | (use_pc[1] != 0b0 & (~ (haveRVC())))) + if (use_pc[0] != bitzero | (use_pc[1] != bitzero & (~ (haveRVC())))) then F_Error(E_Fetch_Addr_Align, PC) else match translateAddr(use_pc, Execute) { TR_Failure(e) => F_Error(e, PC), |