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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2020-01-07 17:09:57 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2020-01-07 17:09:57 -0800 |
| commit | 778301c9a2f483523e83581d7cffb93effb75134 (patch) | |
| tree | 3691b22682552587b8c50b3b63a32a366d6b3274 /model/riscv_fetch.sail | |
| parent | e15f302b12df29014c5dd6d19bbacf12be19ff4d (diff) | |
| parent | dfebc748f8a762718cfda1f1a1201debe754a9c6 (diff) | |
| download | sail-riscv-778301c9a2f483523e83581d7cffb93effb75134.zip sail-riscv-778301c9a2f483523e83581d7cffb93effb75134.tar.gz sail-riscv-778301c9a2f483523e83581d7cffb93effb75134.tar.bz2 | |
Merge branch 'master' into rsnikhil.
Diffstat (limited to 'model/riscv_fetch.sail')
| -rw-r--r-- | model/riscv_fetch.sail | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/model/riscv_fetch.sail b/model/riscv_fetch.sail index 64aff4b..cdda96e 100644 --- a/model/riscv_fetch.sail +++ b/model/riscv_fetch.sail @@ -4,7 +4,7 @@ function isRVC(h : half) -> bool = ~ (h[1 .. 0] == 0b11) -val fetch : unit -> FetchResult effect {escape, rmem, rreg, wmv, wmvt, wreg} +val fetch : unit -> FetchResult effect {escape, rmem, rmemt, rreg, wmv, wmvt, wreg} function fetch() -> FetchResult = /* fetch PC check for extensions: extensions return a transformed PC to fetch, * but any exceptions use the untransformed PC. @@ -22,7 +22,7 @@ function fetch() -> FetchResult = * exceptions. */ match mem_read(Execute(), ppclo, 2, false, false, false) { - MemException(e) => F_Error(E_Fetch_Access_Fault(), PC), + MemException(e) => F_Error(e, PC), MemValue(ilo) => { if isRVC(ilo) then F_RVC(ilo) @@ -36,7 +36,7 @@ function fetch() -> FetchResult = TR_Failure(e, _) => F_Error(e, PC_hi), TR_Address(ppchi, _) => { match mem_read(Execute(), ppchi, 2, false, false, false) { - MemException(e) => F_Error(E_Fetch_Access_Fault(), PC_hi), + MemException(e) => F_Error(e, PC_hi), MemValue(ihi) => F_Base(append(ihi, ilo)) } } |