diff options
| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-06-24 13:57:50 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-06-24 13:57:50 -0700 |
| commit | 295175dd4d510cb416bdc4ef17c2ca96d84ed04e (patch) | |
| tree | bf6841bd4ae27bd92f510b2047da9e8f9c92867a /model/riscv_fetch.sail | |
| parent | 0e589ae548b5326afd085bf176ef5914a326cd8b (diff) | |
| download | sail-riscv-295175dd4d510cb416bdc4ef17c2ca96d84ed04e.zip sail-riscv-295175dd4d510cb416bdc4ef17c2ca96d84ed04e.tar.gz sail-riscv-295175dd4d510cb416bdc4ef17c2ca96d84ed04e.tar.bz2 | |
Narrow the external interface to riscv_mem to mem_{read,write,write_ea}.
Diffstat (limited to 'model/riscv_fetch.sail')
| -rw-r--r-- | model/riscv_fetch.sail | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/model/riscv_fetch.sail b/model/riscv_fetch.sail index 2cc9ea2..b076b95 100644 --- a/model/riscv_fetch.sail +++ b/model/riscv_fetch.sail @@ -21,7 +21,7 @@ function fetch() -> FetchResult = * well as to generate precise fault addresses in any fetch * exceptions. */ - match checked_mem_read(Instruction, ppclo, 2, false, false, false) { + match mem_read(Instruction, ppclo, 2, false, false, false) { MemException(e) => F_Error(E_Fetch_Access_Fault, PC), MemValue(ilo) => { if isRVC(ilo) @@ -35,7 +35,7 @@ function fetch() -> FetchResult = match translateAddr(use_pc_hi, Execute, Instruction) { TR_Failure(e) => F_Error(e, PC_hi), TR_Address(ppchi) => { - match checked_mem_read(Instruction, ppchi, 2, false, false, false) { + match mem_read(Instruction, ppchi, 2, false, false, false) { MemException(e) => F_Error(E_Fetch_Access_Fault, PC_hi), MemValue(ihi) => F_Base(append(ihi, ilo)) } |