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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-05-10 11:04:48 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-05-10 11:04:48 -0700 |
| commit | 374a1e221c32a2856e31dfcd44abf539cc07a425 (patch) | |
| tree | 83dcb91722eac7080b46ade680ada2592b91efd7 /model/riscv_addr_checks.sail | |
| parent | c3bcac091312173ff87beccb7709b5ab0eeccfaa (diff) | |
| download | sail-riscv-374a1e221c32a2856e31dfcd44abf539cc07a425.zip sail-riscv-374a1e221c32a2856e31dfcd44abf539cc07a425.tar.gz sail-riscv-374a1e221c32a2856e31dfcd44abf539cc07a425.tar.bz2 | |
Rename regbits to regidx, to clarify the type is an index and not the contents of a register.
Diffstat (limited to 'model/riscv_addr_checks.sail')
| -rw-r--r-- | model/riscv_addr_checks.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/model/riscv_addr_checks.sail b/model/riscv_addr_checks.sail index 25b6396..28e688d 100644 --- a/model/riscv_addr_checks.sail +++ b/model/riscv_addr_checks.sail @@ -46,7 +46,7 @@ type ext_data_addr_error = unit /* Default data addr is just base register + immediate offset (may be zero). Extensions might override and add additional checks. */ -function ext_data_get_addr(base : regbits, offset : xlenbits, acc : AccessType, rt : ReadType, width : word_width) +function ext_data_get_addr(base : regidx, offset : xlenbits, acc : AccessType, rt : ReadType, width : word_width) -> Ext_DataAddr_Check(ext_data_addr_error) = let addr = X(base) + offset in Ext_DataAddr_OK(addr) |