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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-15 16:49:56 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-02-15 16:49:56 -0800 |
| commit | e5ef555f699af90128d57246801a3d94c6a18854 (patch) | |
| tree | eb88acab79f56b32f82d5dc112ad5c753e80b269 /model/prelude.sail | |
| parent | a38c63600d89057f17164553c20942ffe77b60db (diff) | |
| download | sail-riscv-e5ef555f699af90128d57246801a3d94c6a18854.zip sail-riscv-e5ef555f699af90128d57246801a3d94c6a18854.tar.gz sail-riscv-e5ef555f699af90128d57246801a3d94c6a18854.tar.bz2 | |
More RV32 fixes.
Diffstat (limited to 'model/prelude.sail')
| -rw-r--r-- | model/prelude.sail | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/model/prelude.sail b/model/prelude.sail index 33638aa..bd719fa 100644 --- a/model/prelude.sail +++ b/model/prelude.sail @@ -348,10 +348,6 @@ infix 7 << val operator >> = "shift_bits_right" : forall 'n 'm. (bits('n), bits('m)) -> bits('n) val operator << = "shift_bits_left" : forall 'n 'm. (bits('n), bits('m)) -> bits('n) -val vector64 : int -> bits(64) - -function vector64 n = __raw_GetSlice_int(64, n, 0) - val to_bits : forall 'l, 'l >= 0.(atom('l), int) -> bits('l) function to_bits (l, n) = __raw_GetSlice_int(l, n, 0) |