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author | Xinlai Wan <xinlai.w@rioslab.org> | 2024-04-17 14:07:01 +0800 |
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committer | GitHub <noreply@github.com> | 2024-04-17 14:07:01 +0800 |
commit | 6605792e014d67292c4adc936d789cdea511b3ed (patch) | |
tree | 061692f9a92e9ee37d2940cfde66d7c4bf4c2409 /model/prelude.sail | |
parent | 9692f84f08290d82d6305fb3934f0b0dcb70191c (diff) | |
parent | 16077e126b634c006590b02cb758d48a3882528a (diff) | |
download | sail-riscv-6605792e014d67292c4adc936d789cdea511b3ed.zip sail-riscv-6605792e014d67292c4adc936d789cdea511b3ed.tar.gz sail-riscv-6605792e014d67292c4adc936d789cdea511b3ed.tar.bz2 |
Merge branch 'master' into master
Signed-off-by: Xinlai Wan <xinlai.w@rioslab.org>
Diffstat (limited to 'model/prelude.sail')
-rw-r--r-- | model/prelude.sail | 194 |
1 files changed, 29 insertions, 165 deletions
diff --git a/model/prelude.sail b/model/prelude.sail index 6b5e46c..028af21 100644 --- a/model/prelude.sail +++ b/model/prelude.sail @@ -1,71 +1,9 @@ /*=======================================================================================*/ -/* RISCV Sail Model */ -/* */ /* This Sail RISC-V architecture model, comprising all files and */ -/* directories except for the snapshots of the Lem and Sail libraries */ -/* in the prover_snapshots directory (which include copies of their */ -/* licences), is subject to the BSD two-clause licence below. */ -/* */ -/* Copyright (c) 2017-2023 */ -/* Prashanth Mundkur */ -/* Rishiyur S. Nikhil and Bluespec, Inc. */ -/* Jon French */ -/* Brian Campbell */ -/* Robert Norton-Wright */ -/* Alasdair Armstrong */ -/* Thomas Bauereiss */ -/* Shaked Flur */ -/* Christopher Pulte */ -/* Peter Sewell */ -/* Alexander Richardson */ -/* Hesham Almatary */ -/* Jessica Clarke */ -/* Microsoft, for contributions by Robert Norton-Wright and Nathaniel Wesley Filardo */ -/* Peter Rugg */ -/* Aril Computer Corp., for contributions by Scott Johnson */ -/* Philipp Tomsich */ -/* VRULL GmbH, for contributions by its employees */ -/* */ -/* All rights reserved. */ -/* */ -/* This software was developed by the above within the Rigorous */ -/* Engineering of Mainstream Systems (REMS) project, partly funded by */ -/* EPSRC grant EP/K008528/1, at the Universities of Cambridge and */ -/* Edinburgh. */ -/* */ -/* This software was developed by SRI International and the University of */ -/* Cambridge Computer Laboratory (Department of Computer Science and */ -/* Technology) under DARPA/AFRL contract FA8650-18-C-7809 ("CIFV"), and */ -/* under DARPA contract HR0011-18-C-0016 ("ECATS") as part of the DARPA */ -/* SSITH research programme. */ +/* directories except where otherwise noted is subject the BSD */ +/* two-clause license in the LICENSE file. */ /* */ -/* This project has received funding from the European Research Council */ -/* (ERC) under the European Union’s Horizon 2020 research and innovation */ -/* programme (grant agreement 789108, ELVER). */ -/* */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* 1. Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* 2. Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in */ -/* the documentation and/or other materials provided with the */ -/* distribution. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' */ -/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED */ -/* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A */ -/* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR */ -/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ -/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF */ -/* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND */ -/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, */ -/* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */ -/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF */ -/* SUCH DAMAGE. */ +/* SPDX-License-Identifier: BSD-2-Clause */ /*=======================================================================================*/ default Order dec @@ -74,69 +12,33 @@ $include <smt.sail> $include <option.sail> $include <arith.sail> $include <string.sail> +$include "mapping.sail" $include <vector_dec.sail> $include <regfp.sail> +$include <generic_equality.sail> +$include "hex_bits.sail" -val string_startswith = "string_startswith" : (string, string) -> bool -val string_drop = "string_drop" : (string, nat) -> string -val string_take = "string_take" : (string, nat) -> string -val string_length = "string_length" : string -> nat -val string_append = {c: "concat_str", _: "string_append"} : (string, string) -> string - -val eq_anything = {ocaml: "(fun (x, y) -> x = y)", interpreter: "eq_anything", lem: "eq", coq: "generic_eq", c: "eq_anything"} : forall ('a : Type). ('a, 'a) -> bool - -overload operator == = {eq_string, eq_anything} - -val "reg_deref" : forall ('a : Type). register('a) -> 'a -/* sneaky deref with no effect necessary for bitfield writes */ -val _reg_deref = "reg_deref" : forall ('a : Type). register('a) -> 'a - -val any_vector_update = {ocaml: "update", lem: "update_list_dec", coq: "vector_update"} : forall 'n ('a : Type). - (vector('n, dec, 'a), int, 'a) -> vector('n, dec, 'a) - -overload vector_update = {any_vector_update} - -val update_subrange = {ocaml: "update_subrange", interpreter: "update_subrange", lem: "update_subrange_vec_dec", coq: "update_subrange_vec_dec"} : forall 'n 'm 'o. - (bits('n), atom('m), atom('o), bits('m - ('o - 1))) -> bits('n) - -val vector_concat = {ocaml: "append", lem: "append_list", coq: "vec_concat"} : forall ('n : Int) ('m : Int) ('a : Type). - (vector('n, dec, 'a), vector('m, dec, 'a)) -> vector('n + 'm, dec, 'a) - -overload append = {vector_concat} val not_bit : bit -> bit - function not_bit(b) = if b == bitone then bitzero else bitone overload ~ = {not_bool, not_vec, not_bit} -val not = pure {coq: "negb", _: "not"} : forall ('p : Bool). bool('p) -> bool(not('p)) - -val neq_vec = {lem: "neq"} : forall 'n. (bits('n), bits('n)) -> bool - -function neq_vec (x, y) = not_bool(eq_bits(x, y)) - -val neq_anything = {lem: "neq", coq: "generic_neq"} : forall ('a : Type). ('a, 'a) -> bool - -function neq_anything (x, y) = not_bool(x == y) - -overload operator != = {neq_vec, neq_anything} +// not_bool alias. +val not : forall ('p : Bool). bool('p) -> bool(not('p)) +function not(b) = not_bool(b) overload operator & = {and_vec} overload operator | = {or_vec} -val string_of_int = {c: "string_of_int", ocaml: "string_of_int", interpreter: "string_of_int", lem: "stringFromInteger", coq: "string_of_int"} : int -> string - -val "string_of_bits" : forall 'n. bits('n) -> string - -function string_of_bit(b: bit) -> string = +function bit_str(b: bit) -> string = match b { bitzero => "0b0", bitone => "0b1" } -overload BitStr = {string_of_bits, string_of_bit} +overload BitStr = {bits_str, bit_str} val int_power = {ocaml: "int_power", interpreter: "int_power", lem: "pow", coq: "pow", c: "pow_int"} : (int, int) -> int @@ -164,7 +66,7 @@ overload min = {min_int} overload max = {max_int} -val pow2 = "pow2" : forall 'n. atom('n) -> atom(2 ^ 'n) +val pow2 = "pow2" : forall 'n. int('n) -> int(2 ^ 'n) val print = "print_endline" : string -> unit val print_string = "print_string" : (string, string) -> unit @@ -210,26 +112,35 @@ function bit_to_bool b = match b { bitzero => false } -val to_bits : forall 'l, 'l >= 0.(atom('l), int) -> bits('l) +val to_bits : forall 'l, 'l >= 0.(int('l), int) -> bits('l) function to_bits (l, n) = get_slice_int(l, n, 0) infix 4 <_s +infix 4 >_s +infix 4 <=_s infix 4 >=_s infix 4 <_u -infix 4 >=_u +infix 4 >_u infix 4 <=_u +infix 4 >=_u val operator <_s : forall 'n, 'n > 0. (bits('n), bits('n)) -> bool +val operator >_s : forall 'n, 'n > 0. (bits('n), bits('n)) -> bool +val operator <=_s : forall 'n, 'n > 0. (bits('n), bits('n)) -> bool val operator >=_s : forall 'n, 'n > 0. (bits('n), bits('n)) -> bool val operator <_u : forall 'n. (bits('n), bits('n)) -> bool -val operator >=_u : forall 'n. (bits('n), bits('n)) -> bool +val operator >_u : forall 'n. (bits('n), bits('n)) -> bool val operator <=_u : forall 'n. (bits('n), bits('n)) -> bool +val operator >=_u : forall 'n. (bits('n), bits('n)) -> bool function operator <_s (x, y) = signed(x) < signed(y) +function operator >_s (x, y) = signed(x) > signed(y) +function operator <=_s (x, y) = signed(x) <= signed(y) function operator >=_s (x, y) = signed(x) >= signed(y) function operator <_u (x, y) = unsigned(x) < unsigned(y) -function operator >=_u (x, y) = unsigned(x) >= unsigned(y) +function operator >_u (x, y) = unsigned(x) > unsigned(y) function operator <=_u (x, y) = unsigned(x) <= unsigned(y) +function operator >=_u (x, y) = unsigned(x) >= unsigned(y) infix 7 >> infix 7 << @@ -237,8 +148,8 @@ infix 7 << val "shift_bits_right" : forall 'n 'm. (bits('n), bits('m)) -> bits('n) val "shift_bits_left" : forall 'n 'm. (bits('n), bits('m)) -> bits('n) -val "shiftl" : forall 'm 'n, 'n >= 0. (bits('m), atom('n)) -> bits('m) -val "shiftr" : forall 'm 'n, 'n >= 0. (bits('m), atom('n)) -> bits('m) +val "shiftl" : forall 'm 'n, 'n >= 0. (bits('m), int('n)) -> bits('m) +val "shiftr" : forall 'm 'n, 'n >= 0. (bits('m), int('n)) -> bits('m) overload operator >> = {shift_bits_right, shiftr} overload operator << = {shift_bits_left, shiftl} @@ -264,11 +175,11 @@ val rotate_bits_left : forall 'n 'm, 'm >= 0. (bits('n), bits('m)) -> bits('n) function rotate_bits_left (v, n) = (v << n) | (v >> (to_bits(length(n), length(v)) - n)) -val rotater : forall 'm 'n, 'm >= 'n >= 0. (bits('m), atom('n)) -> bits('m) +val rotater : forall 'm 'n, 'm >= 'n >= 0. (bits('m), int('n)) -> bits('m) function rotater (v, n) = (v >> n) | (v << (length(v) - n)) -val rotatel : forall 'm 'n, 'm >= 'n >= 0. (bits('m), atom('n)) -> bits('m) +val rotatel : forall 'm 'n, 'm >= 'n >= 0. (bits('m), int('n)) -> bits('m) function rotatel (v, n) = (v << n) | (v >> (length(v) - n)) @@ -284,53 +195,6 @@ function reverse_bits_in_byte (xs : bits(8)) -> bits(8) = { overload reverse = {reverse_bits_in_byte} -/* helpers for mappings */ - -val spc : unit <-> string -val opt_spc : unit <-> string -val def_spc : unit <-> string - -val "decimal_string_of_bits" : forall 'n. bits('n) -> string -val hex_bits : forall 'n . (atom('n), bits('n)) <-> string - -val n_leading_spaces : string -> nat -function n_leading_spaces s = - match s { - "" => 0, - _ => match string_take(s, 1) { - " " => 1 + n_leading_spaces(string_drop(s, 1)), - _ => 0 - } - } - -val spc_forwards : unit -> string -function spc_forwards () = " " -val spc_backwards : string -> unit -function spc_backwards s = () -val spc_matches_prefix : string -> option((unit, nat)) -function spc_matches_prefix s = { - let n = n_leading_spaces(s); - match n { - 0 => None(), - _ => Some((), n) - } -} - -val opt_spc_forwards : unit -> string -function opt_spc_forwards () = "" -val opt_spc_backwards : string -> unit -function opt_spc_backwards s = () -val opt_spc_matches_prefix : string -> option((unit, nat)) -function opt_spc_matches_prefix s = - Some((), n_leading_spaces(s)) - -val def_spc_forwards : unit -> string -function def_spc_forwards () = " " -val def_spc_backwards : string -> unit -function def_spc_backwards s = () -val def_spc_matches_prefix : string -> option((unit, nat)) -function def_spc_matches_prefix s = opt_spc_matches_prefix(s) - overload operator / = {quot_round_zero} overload operator * = {mult_atom, mult_int} |