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| author | Tim Hutt <timothy.hutt@codasip.com> | 2023-09-23 19:57:38 +0100 |
|---|---|---|
| committer | Bill McSpadden <bill@riscv.org> | 2023-10-11 20:50:13 -0500 |
| commit | 51a6c967fb320c2d47a3630b1f392e54eb69c3d7 (patch) | |
| tree | cd864017e11911f4e86c32e7a437993a9ce05a58 /handwritten_support | |
| parent | 532714a6c71b47a91176eb90fef3b3b049c52fce (diff) | |
| download | sail-riscv-51a6c967fb320c2d47a3630b1f392e54eb69c3d7.zip sail-riscv-51a6c967fb320c2d47a3630b1f392e54eb69c3d7.tar.gz sail-riscv-51a6c967fb320c2d47a3630b1f392e54eb69c3d7.tar.bz2 | |
Implement menvcfg
This implements the m/senvcfg(h) CSRs. This CSR is used to enable/disable extensions and behaviours for lower privilege modes. Currently the only implemented bit is FIOM which affects how fences work.
It also affects how atomic memory accesses work in non-cacheable regions, but the model does not currently support PMAs so that can't easily be implemented.
Diffstat (limited to 'handwritten_support')
| -rw-r--r-- | handwritten_support/riscv_extras.lem | 4 | ||||
| -rw-r--r-- | handwritten_support/riscv_extras.v | 1 | ||||
| -rw-r--r-- | handwritten_support/riscv_extras_sequential.lem | 4 |
3 files changed, 9 insertions, 0 deletions
diff --git a/handwritten_support/riscv_extras.lem b/handwritten_support/riscv_extras.lem index a476136..5d1fd85 100644 --- a/handwritten_support/riscv_extras.lem +++ b/handwritten_support/riscv_extras.lem @@ -161,6 +161,10 @@ val sys_enable_zfinx : unit -> bool let sys_enable_zfinx () = false declare ocaml target_rep function sys_enable_zfinx = `Platform.enable_zfinx` +val sys_enable_fiom : unit -> bool +let sys_enable_fiom () = true +declare ocaml target_rep function sys_enable_fiom = `Platform.enable_fiom` + val plat_ram_base : forall 'a. Size 'a => unit -> bitvector 'a let plat_ram_base () = wordFromInteger 0 declare ocaml target_rep function plat_ram_base = `Platform.dram_base` diff --git a/handwritten_support/riscv_extras.v b/handwritten_support/riscv_extras.v index 14029ee..c879bf8 100644 --- a/handwritten_support/riscv_extras.v +++ b/handwritten_support/riscv_extras.v @@ -200,6 +200,7 @@ Axiom sys_enable_rvc : unit -> bool. Axiom sys_enable_fdext : unit -> bool. Axiom sys_enable_next : unit -> bool. Axiom sys_enable_zfinx : unit -> bool. +Axiom sys_enable_fiom : unit -> bool. (* The constraint solver can do this itself, but a Coq bug puts anonymous_subproof into the term instead of an actual subproof. *) diff --git a/handwritten_support/riscv_extras_sequential.lem b/handwritten_support/riscv_extras_sequential.lem index 41ca9c6..a7b4899 100644 --- a/handwritten_support/riscv_extras_sequential.lem +++ b/handwritten_support/riscv_extras_sequential.lem @@ -153,6 +153,10 @@ val sys_enable_next : unit -> bool let sys_enable_next () = true declare ocaml target_rep function sys_enable_next = `Platform.enable_next` +val sys_enable_fiom : unit -> bool +let sys_enable_fiom () = true +declare ocaml target_rep function sys_enable_fiom = `Platform.enable_fiom` + val plat_ram_base : forall 'a. Size 'a => unit -> bitvector 'a let plat_ram_base () = wordFromInteger 0 declare ocaml target_rep function plat_ram_base = `Platform.dram_base` |