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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-01-25 20:13:48 -0800 |
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| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-01-25 20:13:48 -0800 |
| commit | fc2e8077d27d6f3964c2775d8a47a9adad3b3030 (patch) | |
| tree | e55f27b2077ec10ea2f93a625e1165589a994385 /doc | |
| parent | 802070807a98ee42d6d5c2933c2f0f1a13ae2509 (diff) | |
| download | sail-riscv-fc2e8077d27d6f3964c2775d8a47a9adad3b3030.zip sail-riscv-fc2e8077d27d6f3964c2775d8a47a9adad3b3030.tar.gz sail-riscv-fc2e8077d27d6f3964c2775d8a47a9adad3b3030.tar.bz2 | |
Mention mstatus.SD handling in the Extending guide.
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/ExtendingGuide.md | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/doc/ExtendingGuide.md b/doc/ExtendingGuide.md index ca5f405..cef9f15 100644 --- a/doc/ExtendingGuide.md +++ b/doc/ExtendingGuide.md @@ -11,7 +11,9 @@ definitions can be added in a separate file. If these registers have properties of control-and-status registers (CSRs), or depend on privilege level (such as hypervisor-mode registers), additional access control checks would need to be provided as is done for the standard -CSRs in `riscv_sys.sail`. +CSRs in `riscv_sys.sail`. In addition, the handling of updates to +`mstatus.XS` and `mstatus.SD` may need to be updated in +`riscv_sys.sail` to handle any extended register state. Adding a new privilege level or functionality restricted by privilege level will normally be accompanied by defining new exception causes |