Unify VM code

Old vmem code had much 'cut-and-paste' replication for RV32 (Sv32) and (#408)

RV64 (Sv39, Sv48), and was scattered over several files.

New code unifies them into single set of parameterized functions
that works for RV32/RV64 and Sv32/Sv39/Sv48 (and is ready for Sv57).

Deleted old files:
    riscv_vmem_rv32.sail    riscv_vmem_rv64.sail
    riscv_vmem_sv32.sail    riscv_vmem_sv39.sail    riscv_vmem_sv48.sail
    riscv_pte.sail
    riscv_ptw.sail

Current files: all named riscv_vmem_*
    riscv_vmem.sail    (root file for vmem)
    riscv_vmem_common.sail
    riscv_vmem_pte.sail
    riscv_vmem_ptw.sail
    riscv_vmem_tlb.sail
    riscv_vmem_types.sail

Modified top-level Makefile accordingly.

Added documentation on new vmem code: doc/notes_Virtual_Memory.adoc

2 files changed, 1146 insertions, 0 deletions

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+           y="111.11807"
+           x="200.02472"
+           sodipodi:role="line">register</tspan><tspan
+           style="font-style:italic;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:2.82222px;line-height:0.95;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:center;writing-mode:lr-tb;text-anchor:middle;stroke-width:0.264583"
+           y="114.22251"
+           x="200.02472"
+           sodipodi:role="line"
+           id="tspan7">satp</tspan></text>
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+       xml:space="preserve"><tspan
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+         style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:2.82222px;font-family:sans-serif;-inkscape-font-specification:sans-serif;font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;writing-mode:lr-tb;text-anchor:start;stroke-width:0.264583"
+         y="147.06259"
+         x="115.48001"
+         sodipodi:role="line">readCSR()</tspan></text>
+    <text
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+       y="152.38425"
+       x="114.99237"
+       style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:3.52778px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:sans-serif;font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.264583"
+       xml:space="preserve"><tspan
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+         style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:2.82222px;font-family:sans-serif;-inkscape-font-specification:sans-serif;font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;writing-mode:lr-tb;text-anchor:start;stroke-width:0.264583"
+         y="152.38425"
+         x="114.99237"
+         sodipodi:role="line">writeCSR()</tspan></text>
+    <text
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+       x="118.3431"
+       style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:3.52778px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:sans-serif;font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.264583"
+       xml:space="preserve"><tspan
+         id="tspan2"
+         style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:2.82222px;font-family:sans-serif;-inkscape-font-specification:sans-serif;font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;writing-mode:lr-tb;text-anchor:start;stroke-width:0.264583"
+         y="127.36551"
+         x="118.3431"
+         sodipodi:role="line">Exec Fetch</tspan></text>
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+       y="162.47141"
+       x="106.89098"
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+       xml:space="preserve"><tspan
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+         style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:2.82222px;font-family:sans-serif;-inkscape-font-specification:sans-serif;font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;writing-mode:lr-tb;text-anchor:start;stroke-width:0.264583"
+         y="162.47141"
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+         sodipodi:role="line">Exec SFENCE.VMA</tspan></text>
+    <text
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+         id="tspan5">PUBLIC</tspan></text>
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+       y="154.81339"
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+       xml:space="preserve"><tspan
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+         y="154.81339"
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+         sodipodi:role="line">legalize_satp()</tspan></text>
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+    <path
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+       xml:space="preserve"><tspan
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+         style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:2.82222px;font-family:sans-serif;-inkscape-font-specification:sans-serif;font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;writing-mode:lr-tb;text-anchor:start;stroke-width:0.264583"
+         y="129.33925"
+         x="140.94533"
+         sodipodi:role="line">translateAddr()</tspan></text>
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+       xml:space="preserve"><tspan
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+         sodipodi:role="line">union TR_Result</tspan></text>
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+    <path
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+       xml:space="preserve"><tspan
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+         sodipodi:role="line">translate()</tspan></text>
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+       xml:space="preserve"><tspan
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+         y="152.201"
+         x="241.45401"
+         sodipodi:role="line">add_to_TLB()</tspan></text>
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+       y="152.201"
+       x="216.80208"
+       style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:3.52778px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:sans-serif;font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.264583"
+       xml:space="preserve"><tspan
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+         style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:2.82222px;font-family:sans-serif;-inkscape-font-specification:sans-serif;font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;writing-mode:lr-tb;text-anchor:start;stroke-width:0.264583"
+         y="152.201"
+         x="216.80208"
+         sodipodi:role="line">write_TLB()</tspan></text>
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+       y="129.06493"
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+         sodipodi:role="line">mem_read_priv()</tspan></text>
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+         y="154.67165"
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diff --git a/doc/notes_Virtual_Memory.adoc b/doc/notes_Virtual_Memory.adoc
new file mode 100644
index 0000000..fba39a1
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+++ b/doc/notes_Virtual_Memory.adoc
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+= Notes on the Virtual Memory part Sail RISC-V Spec
+
+NOTE: this is an AsciiDoc document and can be processed into
+      browser-readable HTML by the free, open-source tool
+      `asciidoctor`.
+
+NOTE: If you are a code maintainer, kindly update this document if
+      there are any significant developements in vmem code.
+
+This is a commentary/reader's guide to the virtual memory ("vmem")
+code in the Sail RISC-V Formal Spec ("Golden Model").  The primary
+vmem specification code is in file:
+
+    model/riscv_vmem.sail
+
+Additional files:
+
+    model/riscv_vmem_common.sail
+    model/riscv_vmem_pte.sail
+    model/riscv_vmem_ptw.sail
+    model/riscv_vmem_tlb.sail
+    model/riscv_vmem_types.sail
+
+`riscv_vmem_common.sail` contains the parameterization for Sv32, Sv39,
+Sv48 and Sv57.
+
+`riscv_vmem_pte.sail` describes Page Table Entries, checks for
+permission bits, etc.
+
+`riscv_vmem_ptw.sail` describes Page Table Walk exceptions.
+
+`riscv_vmem_tlb.sail` implements a simple TLB (Translation Look-Aside
+Buffer).  TLBs are not part of the RISC-V architecture spec.
+Nevertheless, it is useful to model at least a minimal TLB so that we
+can demonstrate and test SFENCE.VMA functionality (without TLBs,
+SFENCE.VMA is a no-op and there's nothing to test).
+
+TLBs are also useful for sail-riscv model simulation speed.  Without a
+TLB, every Fetch and Load/Store/AMO in virtual memory mode requires a
+full page table walk.  Speed matters mostly for large simulations
+(e.g., Linux-boot can speed up from tens of minutes to a few minutes).
+
+The main vmem code in `riscv_vmem.sail` is structured and commented to
+make it is easy to ignore/skip TLB-related parts.
+
+`riscv_vmem_types.sail` concerns non-standard extensions to the vmem
+system and can be ignored (it is used, e.g., by U.Cambridge's CHERI
+system).
+
+// SECTION ================================================================
+== Simplified call graph
+
+The following figure shows a rough call graph, and this can serve as a
+guide for understanding the code.
+
+image::./figs/notes_Virtual_Memory_Fig1.svg[align="center"]
+
+The yellow rectangle(s) represent the code in `riscv_vmem.sail`, and
+the grey rectangle(s) represent the code in `riscv_vmem_tlb.sail`.  In
+each case, the lighter outer rectangle shows the publicly visible
+resources ("API"), and the darker inner rectangle shows internal
+(private) resources.
+
+On the left are shown the external places from which the vmem code is
+invoked, using its public resources.  On the right are shown the
+external resources used by the vmem code.
+
+The main flow (ignoring TLBs) is at the top: The external execution
+code for instruction fetch, load, store and AMO invoke
+`translateAddr()` and receive a result of `TR_Result` type.
+`translateAddr()`, in turn, invokes `translate()`,
+`translate_TLB_miss()` and `pt_walk()`; the latter invokes the
+external `mem_read_priv()` to read PTEs (Page Table Entries) from
+memory.  The SATP register lives in this vmem code, and is accessed by
+the external general `readCSR()` and `writeCSR()` functions.
+
+`translate()` invokes `lookup_TLB()` and, if a hit, invokes
+`translate_TLB_hit()`, avoiding a page-table walk (and therefore no
+reads from memory).
+
+`mem_write_value_priv()` is called for writing back, to memory, PTEs
+(Page Table Entries) whose A and/or D bits have been modified as part
+of the access.
+
+// SECTION ================================================================
+== Status
+
+* 2024-02-18: Many stylistic updates based on PR comments.
+
+* 2023-11-30: Passing all ISA tests in `tests/riscv-tests` (163 for
+  RV32 and 229 for RV64, about half of which run with Virtual Memory).
+  Also passing 712 tests in GitHub CI flow.
+
+* 2023-11-30: Sv57 not yet implemented (the code has placeholders
+  for Sv57 support; search for "Sv57")
+
+* 2023-11-30: Sv48 or Sv57 have not been tested; we do not have any tests for them.
+
+// SECTION ================================================================
+== Diary notes
+
+2019: Original code written, primarily by https://github.com/pmundkur[@pmundkur]
+
+2023-11: Refactored by https://github.com/rsnikhil[@rsnikhil] for:
+
+* Unifying previously separate RV32/RV64, Sv32/Sv39/Sv57 code into a
+  single, parameterized code.
+* Misc. stylistic improvements.
+* Deleted older files:
++
+    riscv_pte.sail
+    riscv_ptw.sail
+    riscv_vmem_common.sail
+    riscv_vmem_rv32.sail
+    riscv_vmem_rv64.sail
+    riscv_vmem_sv32.sail
+    riscv_vmem_sv39.sail
+    riscv_vmem_sv48.sail
++