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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-07-18 13:41:04 -0700 |
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| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-07-18 13:41:04 -0700 |
| commit | 8cbb3f3f3d767b3d791ea4f4f348ed2e92210253 (patch) | |
| tree | 4d6f93aaa823ed64a0c0e36bcf829f0407e8923d /doc | |
| parent | 93eb67eebdb100b4f5d1e5ceab64ba194030d9f8 (diff) | |
| download | sail-riscv-8cbb3f3f3d767b3d791ea4f4f348ed2e92210253.zip sail-riscv-8cbb3f3f3d767b3d791ea4f4f348ed2e92210253.tar.gz sail-riscv-8cbb3f3f3d767b3d791ea4f4f348ed2e92210253.tar.bz2 | |
Minor tweaks.
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/ReadingGuide.md | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/doc/ReadingGuide.md b/doc/ReadingGuide.md index 152267f..a371388 100644 --- a/doc/ReadingGuide.md +++ b/doc/ReadingGuide.md @@ -128,7 +128,9 @@ Sail model. The OCaml emulator follows the same approach. <img src="figs/riscvcsimdeps.svg"> The nodes that are not colored are the handwritten C files for the C -emulator. +emulator. The black arrows indicate dependency relationships, while +the red arrow indicates a file generated by the Sail compiler from +Sail source files. `riscv_sim` is the top level file for the C emulator: it processes command line options, initializes the platform model with any ISA @@ -138,9 +140,10 @@ boot loader and DeviceTree binary blobs, and initializes the memory map. The generated C model `riscv_model_$ARCH` is built from the Sail -sources by the Sail compiler. It contains calls to the platform -interface `riscv_platform` for platform-specific information; the -latter is typically defined as externally specified in the Sail file +sources by the Sail compiler for the specified architecture $ARCH, +either RV32 or RV64. It contains calls to the platform interface +`riscv_platform` for platform-specific information; the latter is +typically defined as externally specified in the Sail file `riscv_platform.sail`. The Sail system provides a C library for use with its C backend, which |