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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2020-09-05 07:32:39 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2020-09-05 07:33:52 -0700 |
| commit | 3d0957ac99b7875e4bd11203b24cec5715980d0b (patch) | |
| tree | 09ed5fa9b61d0253159106a9a47aa73a88e2ae3a /doc | |
| parent | c138a086f91552bc158f3bfab9a52221a0819171 (diff) | |
| download | sail-riscv-3d0957ac99b7875e4bd11203b24cec5715980d0b.zip sail-riscv-3d0957ac99b7875e4bd11203b24cec5715980d0b.tar.gz sail-riscv-3d0957ac99b7875e4bd11203b24cec5715980d0b.tar.bz2 | |
Update status and docs for hints.
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/ReadingGuide.md | 2 | ||||
| -rw-r--r-- | doc/Status.md | 4 |
2 files changed, 2 insertions, 4 deletions
diff --git a/doc/ReadingGuide.md b/doc/ReadingGuide.md index 1e77a33..5c8d0f6 100644 --- a/doc/ReadingGuide.md +++ b/doc/ReadingGuide.md @@ -102,6 +102,8 @@ such as the platform memory map. are represented as a clause of the `execute` function. `mapping` clauses specify the encoding and decoding of each instruction to and from their binary representations and assembly language formats. + Hint instructions that are not implicitly handled elsewhere are + explicitly handled in `riscv_insts_hints.sail`. - `riscv_fetch.sail` contains the instruction fetch function. It supports checking and transformation of the fetch address as diff --git a/doc/Status.md b/doc/Status.md index 57a044c..539020a 100644 --- a/doc/Status.md +++ b/doc/Status.md @@ -42,10 +42,6 @@ specification. - The RV128 primary base ISA. -- An explicit and complete definition of the HINT instructions. As - currently implemented, some of them are implicitly implemented as - NOPs. - - Specification and implementation of Endianness Control. - Support for changing XLEN or base ISA control using the {M,S,U}XL |