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| author | Peter Sewell <Peter.Sewell@cl.cam.ac.uk> | 2019-09-12 07:18:46 +0100 |
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| committer | Peter Sewell <Peter.Sewell@cl.cam.ac.uk> | 2019-09-12 07:18:46 +0100 |
| commit | 23b0067819f7b05b07a7b26a71dd3cd8f4ee85b2 (patch) | |
| tree | 6e86abceb868bdd54cb91627f5d423d313f11d65 /doc | |
| parent | 4817059f90df4ea862879b8639f5e5fa58472ed4 (diff) | |
| download | sail-riscv-23b0067819f7b05b07a7b26a71dd3cd8f4ee85b2.zip sail-riscv-23b0067819f7b05b07a7b26a71dd3cd8f4ee85b2.tar.gz sail-riscv-23b0067819f7b05b07a7b26a71dd3cd8f4ee85b2.tar.bz2 | |
tweak Status page
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/Status.md | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/doc/Status.md b/doc/Status.md index 68e016b..fc4d44a 100644 --- a/doc/Status.md +++ b/doc/Status.md @@ -1,5 +1,4 @@ -The following is a list of ISA features that are currently captured in -the Sail specification. +The Sail specification currently captures the following ISA features: - The RV32I and RV64I primary base ISAs. @@ -16,8 +15,8 @@ the Sail specification. - Physical Memory Protection (PMP) -For the status of the RVWMO memory consistency model, please see [the -RMEM project](https://github.com/rems-project/rmem). +For the RVWMO memory consistency model, this Sail ISA semantics is integrated with the RVWMO operational model in [the +RMEM tool](https://github.com/rems-project/rmem). The Sail specification is parameterized over the following platform-specific options: @@ -30,8 +29,8 @@ platform-specific options: - the contents of the `mtval` register on an illegal instruction exception. -The following is a list of ISA features that are specified in the -prose ISA specification but that are not yet implemented in the Sail +The following ISA features are specified in the +prose RISC-V ISA specification but not currently in the Sail specification. - The RV32E and RV64E subsets of the primary base RV32I and RV64I @@ -48,7 +47,7 @@ specification. - Specification and implementation of Endianness Control. -- A complete implementation of all hardware performance counters. +- A complete definition of all hardware performance counters. These are used to count platform-specific events, and hence platform-dependent. |