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| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-09-11 16:31:53 -0700 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2019-09-11 16:44:45 -0700 |
| commit | b9c136aac38b2afae1ddc9b205975e6002a60846 (patch) | |
| tree | 36cac3f644212b74d7ca20716fa5e5cf9f845c79 /doc/figs/riscvspecdeps.tex | |
| parent | a999811942f542099765cd5024954960c4a6c7f9 (diff) | |
| download | sail-riscv-b9c136aac38b2afae1ddc9b205975e6002a60846.zip sail-riscv-b9c136aac38b2afae1ddc9b205975e6002a60846.tar.gz sail-riscv-b9c136aac38b2afae1ddc9b205975e6002a60846.tar.bz2 | |
Update the docs for the virtual memory and exception-code extensions.
Diffstat (limited to 'doc/figs/riscvspecdeps.tex')
| -rw-r--r-- | doc/figs/riscvspecdeps.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/doc/figs/riscvspecdeps.tex b/doc/figs/riscvspecdeps.tex index 1d937e5..212f477 100644 --- a/doc/figs/riscvspecdeps.tex +++ b/doc/figs/riscvspecdeps.tex @@ -34,8 +34,8 @@ % compute location for virtmem \coordinate (vmloc) at ($(types)!3!(pmp)$); \node (virtmem) [spec] at (vmloc) {\textbf{virtual memory}\\ - PTE formats, TLB (\texttt{riscv\_vmem\_common})\\ - page table walks (\texttt{riscv\_vmem\_svNN})\\ + PTE formats, TLB (\texttt{riscv\_vmem\_\{types,common\}})\\ + page table walks (\texttt{riscv\_types\_ext},\texttt{riscv\_vmem\_svNN})\\ address translation (\texttt{riscv\_vmem\_rvNN})}; |